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TSMC to Boost 4nm & 5nm Output by 25%: Ada Lovelace, Hopper, RDNA 3, Zen 4

Silicon wafer
(Image credit: TSMC)

For the last few years, TSMC's N5 nodes have been used almost exclusively by Apple for its system-on-chips aimed at smartphones and PCs. But as more companies adopt these fabrication technologies, TSMC has had to increase its production capacities. A new report says that TSMC will increase its N5 production capacity by around 25% this year to meet the demand for N5 chips from the likes of AMD, Nvidia, and MediaTek.

TSMC's N5 (5nm-class) family of manufacturing processes includes vanilla N5, performance-enhanced N5P, N4, N4P, N4X, and Nvidia-specific 4N. Apple is believed to use N5 and N5P for its existing A14, M1, and A15 system-on-chips, but companies like AMD, MediaTek, and Nvidia, are set to use various technologies from the lineup. Meanwhile, Apple's next-generation A16 is also projected to migrate to N4.

For example, Nvidia has tapped 4N for its Hopper compute GPUs (and perhaps for Ada Lovelace consumer GPUs), whereas MediaTek uses N5 for its Dimensity 8000/8100 and will use N4 for Dimensity 9000. 

With N5, TSMC has the capacity for up to 120,000 wafer starts per month (WSPM), according to a report by DigiTimes. 120,000 N5 WSPM is what TSMC planned to achieve by early 2022, so the foundry has the exact capacity it planned to have. However, to serve its existing and future customers interested in one of N5 processes, TSMC will install some additional equipment to increase N5 output to 150,000 WSPM by Q3 2022, DigiTimes claims. Indeed, TSMC will need more N5-capable tools at its fabs by mid-2022.

Nvidia plans to start shipping its Hopper compute GPUs commercially in Q3, so given the length of modern cycles, we're pretty sure that TSMC is already ramping H100 production using the Nvidia-tailored N4 node. While the production volumes dedicated to these GPUs isn't very high, the chips are very large, meaning they'll eat a significant share of TSMC's N5-capable capacity. 

Meanwhile, Apple traditionally ramps up its new iPhone SoCs in April or May, so expect TSMC to kick off production of A16 in the coming weeks. Apple's smartphone SoCs are used for hundreds of millions of devices, so Apple will remain TSMC's biggest customer both in terms of revenues and in terms of processed wafers. Also, since MediaTek sells a boatload of advanced SoCs these days, it will need tens of millions of its Dimensity 8000/8100/9000 application processors and will therefore remain TSMC's No. 2 customer. 

We also fully expect AMD to introduce its next-generation Zen 4-based Epyc and Ryzen CPUs along with RDNA 3-based Radeon RX 7000-series GPUs this fall. Nvidia will also launch its Ada Lovelace-powered GeForce RTX 40-series consumer offerings around the same time as well. All of these products are meant to be widely available, so TSMC will need a lot of capacity to produce these chips. 

So far, both AMD and Nvidia have spent billions of dollars on securing production capacity at TSMC to ensure that they can get all the chips they need. As a result, all the capacity that TSMC will add has essentially been paid for already, months before it goes online.

Meanwhile, TSMC plans to kick off mass production of chips using its next-generation N3 node (3nm-class) sometime in the middle of the year. Apple will be the first to adopt this node, and Intel is expected to follow. The first N3 products will be shipped in 2023, so we won't see them in 2022. 

Anton Shilov is a Freelance News Writer at Tom’s Hardware US. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

  • watzupken
    The question is whether 25% increase in production is sufficient to cope with demand. Now that Qualcomm, Intel and Nvidia are on TSMC, the increase in production ramp up may not be enough to satisfy the extra big players. And since Apple is also stuck on 4/5nm and uses TSMC exclusively, so you can imagine how competitive and expensive the node allocation will be.
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