Samsung is currently in the process of developing next-gen 3D DRAM on American soil, says The Korea Times, according to its own industry sources. The lab for this next-gen 3D DRAM development is based in Silicon Valley, operating under the "Device Solutions America" division, or DSA for short.
Apparently, the goal of this lab is to develop an upgraded DRAM model that will allow Samsung to take leadership of the global 3D DRAM market— that's, again, according to Korea Times' reporting on the matter.
For those unfamiliar, "3D DRAM" refers to DRAM being manufactured with a "3D" process. The goal of 3D manufacturing processes is to make better use of physical hardware restraints by "stacking" dies, memory modules, etc on top of each other. Over in the world of CPUs, for example, we have something called "3D Cache", which refers to regular CPU L3 cache that's "stacked" in manufacturing to improve onboard memory capacity. And of course, Samsung pioneered 3D stacked NAND (Samsing calls it V-NAND) for SSD storage more than a decade ago.
As the benefits of 3D cache on desktop CPUs have already demonstrated themselves, Samsung's comments on the improvements offered by 3D DRAM seem quite promising. Korea Times reports a Samsung comment made in October 2023, where they claimed that new structures for sub-10nm DRAM will allow for larger single-chip capacities that can exceed 100 gigabits.
In short, Samsung's work on 3D DRAM could very much be pushing the envelope forward in terms of memory capacity. 3D stacking in CPU manufacturing for increased L3 cache is already proven to work as a method of dramatically boosting capacity, and performance in that constrained workload.
While most modern consumer PCs are hardly hurting for more DRAM, Samsung continuing to push the envelope forward should prove beneficial to the computing market at large. Server operators and the highest-end enthusiasts would benefit first, but normalizing 3D DRAM should serve to both boost the high-end of RAM capacities and lower the cost for the entry-level, as most major advances in PC hardware do.
Time will tell just how successful and dominant Samsung's 3D DRAM will become, though, and exactly how long we'll have to wait for these solutions to become available. For now, we'll just have to be satisfied in know Samsung's Silicon Valley lab is working to push the apparent next generation of DRAM manufacturing forward.
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Doesn't 3D stacking also improve performance?Reply
While most modern consumer PCs are hardly hurting for more DRAM, Samsung continuing to push the envelope forward should prove beneficial to the computing market at large.We want more for less. Let's get 1 TB DIMMs/CAMMs for consumers.
"3D DRAM" refers to DRAM being manufactured with a "3D" process. The goal of 3D manufacturing processes is to make better use of physical hardware restraints by "stacking" dies, memory modules, etc on top of each other. Over in the world of CPUs, for example, we have something called "3D Cache", which refers to regular CPU L3 cache that's "stacked" in manufacturing to improve onboard memory capacity. And of course, Samsung pioneered 3D stacked NAND (Samsing calls it V-NAND) for SSD storage more than a decade ago.First, V-NAND isn't merely die-stacking. This article from 2017 explains how Samsung fit 512 GB into a package by stacking 8x 64-layer V-NAND dies.
Second, die-stacked DRAM isn't new. Server DIMMs had it, going back at least as far as DDR4. HBM uses die-stacked DRAM, and that's been around for about a decade. Most recently, I believe Apple has been using die-stacked memory, in its M-series SoCs. So, let's assume they're not talking about "simple" die-stacking, here.
Probably the most plausible explanation is here:
It was in 2021 that Korean semiconductor makers officially started to talk about 3D DRAM development. It coincided with the time when Samsung Electronics started research by establishing a next-generation process development team within its DS Division in 2021.
3D DRAM is a memory chip with a new structure that breaks the current aged paradigm. Existing DRAM product development focuses on increasing integration by reducing circuit line widths, but as line widths entered the 10 nm range, physical limitations such as capacitor current leaks and interference increased significantly. In order to prevent this, new materials and equipment such as high dielectric constant (high K) deposition materials and extreme ultraviolet (EUV) equipment were introduced. But the semiconductor industry believes that miniaturization to make 10 nm or more advanced chips will cause great challenges for chipmakers.
The line width of cutting-edge DRAM that Samsung Electronics and SK Hynix will mass-produce this year is 12 nanometers. Considering the current situation where the line width of DRAM miniaturization is being reduced by one nanometer, commercialization of DRAM with a new structure will become a necessity, not an option, three to four years from now.
So, I think they're pretty clearly talking about building multiple layers of DRAM cells within a die. Either that, or at least changing the shape of the cells to be more vertically-structured, in order to increase the areal density of a single layer.
A related-sounding (but probably different) effort I recall reading was about Samsung (I think) partnering with Nvidia, to build processing dies that sit at the base of HBM-like DRAM stacks. I'm pretty sure I saw an article about it on here, but I'm unable to find it right now.
Please use the correct unit: 512 GB.bit_user said:This article from 2017 explains how Samsung fit 512 Gb into a package by stacking 8x 64-layer V-NAND dies.
Okay, it seems the article talks about both 512 Gb dies and 512 GB packages (8 bits in a byte lines up with 8 dies per package, making it easy to miss). Sorry for the confusion.usertests said:Please use the correct unit: 512 GB.
Anyway, the key point is that V-NAND is much more (if not entirely) about multi-layer than multi-die.