Chinese chipmaker ships record-breakers: YMTC quietly begins shipping 5th Gen 3D TLC NAND
Well, kind of.

Yangtze Memory Technologies Co. (YMTC) has quietly started to ship its 5th-Gen 3D NAND memory with 294 layers in total as well as 232 active layers, and analysts from TechInsights have managed to obtain these ICs for analysis, reports @Jukanlosreve. As it turns out, YMTC has successfully increased bit density to the levels of its industry peers, while it also achieved the highest vertical gate density — despite sanctions against the company imposed by the U.S.
There are a couple of catches, however.
The chip achieves a remarkable total number of layers (or gates per vertical NAND string) — 294 — which TechInsights says is the highest for current commercial products. The number of active layers of YMTC's 5th Generation 3D NAND is expected to be 232, the same as in the case of the company's 4th-Gen 3D NAND, which has 253 layers in total. The increase in the total number of layers could be a way to improve yield by increasing redundancy or enabling certain features.
Like its predecessors, the 3D NAND device uses string stacking. However, it is unclear whether Yangtze Memory uses two ~147-layer arrays or multiple arrays with fewer layers. In any case, the 294 layers (including active and dummy layers) are an important milestone for YMTC and the whole flash memory industry.
Generation | Model | Organization | Architecture | Active Layers | Total Layers | String Stacking | String Stacking (Total Layers) |
G1 | X0-A030 | MLC | Conventional | 32 | 39 | - | - |
G2 | X1-9050 | TLC | Xtacking 1.0 | 64 | 73 | - | - |
G3 | X2-9060 | TLC | Xtacking 1.0 | 64 | 73 | - | - |
G3 | X2-6070 | QLC | Xtacking 2.0 | 128 | 141 | 2x64L | L69+U72 |
G4 | Test | - | Xtacking 3.0 | 192/196 | 196 | ? | ? |
G4 | X3-9060 | TLC | Xtacking 3.0 | 128 | 141 | 2x64L | L69+U72 |
G4 | X3-9070 | TLC | Xtacking 3.0 | 232 | 253 | 2x116L | L128+U125 |
G4 | X3-6070 | QLC | Xtacking 3.0 | 128 | ? | 2x64L | ? |
G5 | X4-9060 | TLC | Xtacking 4.0 | 128 | ? | 2x64L | ? |
G5 | X4-9070 | TLC | Xtacking 4.0 | 232 | ? | 2x116L | ? |
G6 (?) | ? | TLC | ? | 232 | ? | ? | Row 11 - Cell 7 |
232 active layers is not a record layer count for 3D NAND, but it is in line with the rivals. Only SK hynix's 321-layer 9th Generation 3D NAND has more than 300 active layers these days, though its shipments will start in the first half of this year. The achievement of 294 total layers (or gates per vertical NAND string) not only positions YMTC as a strong contender in the global NAND flash memory market but also signals significant progress in China's semiconductor industry amid major U.S. sanctions.
In terms of bit density, YMTC's 5th Gen 3D TLC device surpasses 20 Gb/mm², which seems to be in line with what SK hynix's G9 3D TLC NAND IC offers and is just slightly below the 22.9 Gb/mm² featured by Kioxia's/Western Digital BiCS8 3D QLC NAND device, according to TechInsights. YMTC's competitors have yet to introduce 3D TLC NAND chips with density levels similar to those of the market.
Header Cell - Column 0 | YMTC | YMTC | Micron | Samsung | WD/Kioxia | SK hynix |
---|---|---|---|---|---|---|
Generation | ? | Xtacking 3.0/Gen 4 | Gen 9 (G9) | V9 | BiCS 8 | Gen 9 |
Number of Layers | 232-Layer | 232-Layer | 276-Layer | 290-Layer (?) | 218-Layer | 321-Layer |
Density per square mm | >20 Gb mm^2 | 19.8 Gb mm^2 | 21.0 Gb mm^2 | 17 Gb mm^2 | 22.9 Gb mm^2 (?) | 20 mm^2 |
Architecture | TLC | QLC | TLC | TLC | QLC | TLC |
Die Capacity | 1 Tb | 1 Tb | 1 Tb | 1 Tb | 2 Tb | 1 Tb |
Interface Speed | ? | ? | Up to 3600 MT/s | Up to 3200 MT/s | Up to 3600 MT/s | ? |
Next-Gen (release date) | ? | Xtacking 4.0 (?) | (unknown) | 3xx (unknown) | ? | ? |
With its 5th Generation 232-layer 3D TLC NAND devices, Yangtze Memory continues to use hybrid bonding technology to connect the flash array with CMOS logic and interface, which enables the company to maximize storage density and I/O performance for the best SSDs that usually surpasses what is offered by rivals. YMTC's 3D TLC NAND ICs use Xtacking 4.0 architecture.
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YMTC's 232-layer 3D NAND with 294 gates per NAND string marks a significant milestone for the company specifically and the Chinese memory industry more broadly. It is noteworthy that Yangtze Memory has not formally announced its 5th Generation 3D TLC NAND devices but has instead quietly begun their volume shipments. This move was possibly made to avoid drawing the attention of the U.S. government and risking further sanctions.
Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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pnx The Micron 2650 SSD (released in August 2024) uses Micron's new 276-layer TLC NAND with a density of roughly 21 Gb/mm^2,Reply
One might think that the table indicates that Micron is stuck at 232 layers, which is not true. -
Pierce2623 Flash memory/dram isn’t under quite as much pressure as logic chips with the export control sanctions because absolutely bleeding edge memory is only at 10nm instead of 2nm. On the other hand, most memory companies use EUV already at 10nm.Reply -
das_stig happy if they make them cheap as chips and with big capacity in 2.5" format, if reliable and comparable performance.Reply -
Pierce2623 Ehh you canReply
Ehh you can keep your 550MB/sec 2.5” form factor. I can get six times the peak read/write speed at better prices out of pcie3 nvme drives. Or for similar prices to SATA 2.5” dtives I could get pcie4 m.2s with 10x the peak read/write speed with an even larger advantage in IOPS.das_stig said:happy if they make them cheap as chips and with big capacity in 2.5" format, if reliable and comparable performance. -
das_stig
Yes, but I want 2.5" format for my servers and plenty of people still use NAS with 2.5".Pierce2623 said:Ehh you can
Ehh you can keep your 550MB/sec 2.5” form factor. I can get six times the peak read/write speed at better prices out of pcie3 nvme drives. Or for similar prices to SATA 2.5” dtives I could get pcie4 m.2s with 10x the peak read/write speed with an even larger advantage in IOPS.