HSIO Lanes And Connectivity
Intel has been using a similar technology to HSIO (high-speed I/O) lanes (Flex /IO on Haswell-based chipsets) to interface between add-ins for years. Compared to its Haswell- and Broadwell-based platforms, however, Skylake is even more reliant on this technology, which sometimes makes understanding the connectivity options of each chipset more confusing.
Nearly every connection between the PCH and another device uses HSIO lanes. The only major connections that don’t are the USB 2.0 ports and the link between DMI link between the CPU and PCH. All USB 3.0 ports, SATA interfaces and PCIe slots consume at least one HSIO lane.
For example, Z170 exposes a total of 26 HSIO lanes, six of which are consumed by six permanently-enabled USB 3.0 ports. So, the chipset ends up with 20 configurable HSIO lanes that can be assigned to other devices. Each SATA port uses an HSIO lane as well, unless it's connected through a third-party controller (though that controller would need at least one lane to communicate with the PCH). As you can see in the diagram, GbE controllers and PCIe-based SSDs also consume available HSIO lanes.
The confusion happens when you hear what the chipset can support. Yes, you can do up to 10 USB 3.0 ports, eight SATA 6Gb/s ports, 20 PCIe 3.0 lanes and gigabit Ethernet. But the platform can only handle some of those I/O options simultaneously.
|Skylake Chipsets (Real) PCIe Connectivity|
|Max PCIe 3.0 Lanes||Max PCIe 3.0 Lanes If All USB, SATA & Single GbE In Use||DMI|
|H110||6 (PCIe 2.0)||6 (PCIe 2.0)||2.0|
The biggest issue is that the maximum number of PCIe 3.0 lanes on each chipset will likely never be exposed. In order to have 20 lanes configured, which is technically possible on Z170, Q170 and C236, you would have to give up all SATA-based storage, native GbE and USB 3.0 ports beyond the six hard-wired ones.
Motherboard manufacturers make the situation more difficult to explain by launched products with more physical connections than the PCH can support at any one time. Engineers make all of the I/O functional by tying multiple devices to a single HSIO lane. Devices that share a lane cannot function simultaneously. So, often, connecting one piece of hardware disables other ports or features elsewhere. And it doesn't help that board vendors don't make this well-known. Most of the spec sheets we've seen do spell out which connections share HSIO lanes, but it's sometimes hidden in fine print somewhere at the bottom. As a result, even enthusiasts get caught buying motherboards based on their connectivity options without realizing they can't all be used together.