Rapidus, a Japanese government-funded startup chipmaker that aims to start production of 2nm chips in 2027, is collaborating with the University of Tokyo and France's Leti research institute to develop 1nm – 1.4nm (1 angstrom - 1.4 angstroms) process technologies reports Nikkei. According to the report, this partnership will initially involve staff exchanges and some fundamental research sharing starting next year.
Under the undisclosed terms of the purported collaboration, Leti will explore novel transistor structures, whereas Rapidus and other Japanese partners will send in scientists and then assess and test prototypes. Rapidus reportedly sets modest goals for its 1nm-class manufacturing processes as it plans to improve power efficiency and performance by 10% to 20% compared to [presumably its own] 2nm fabrication technology. Mainstream adoption of 1nm process technology will happen in the 2030s, following the adoption of 2nm, 1.8nm, and 1.4nm nodes this decade.
Meanwhile, some expect that 1nm and sub-1nm production nodes will require a new transistor structure, and several chipmakers anticipate that vertically-stacked complementary field effect transistors (CFETs) will eventually replace gate-all-around FETs that are yet to enter prime time.
Leti and the Leading-Edge Semiconductor Technology Center (LSTC), a Japanese organization with Rapidus, the University of Tokyo, Riken Research Institute, and some other national universities, signed a memorandum of understanding to explore a partnership back in October. The main point of the MOU is to establish a long-term sustainable semiconductor technology collaboration 'over the next decade and to jointly define long-term R&D roadmaps.'
Rapidus is already engaged with IBM and Belgium's Imec to design a 2nm fabrication process, initiate pilot 2nm chip production in 2025, and ramp up high-volume production of 2nm chips in 2027. Collaborating with Leti does not exclude IBM and Imec from further partnerships with Rapidus and LSTC. In fact, the organizations might just complement each other. This collaboration with global partners can be observed as another vital step to revitalize Japan's position in the semiconductor industry.
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Anton Shilov is a Freelance News Writer at Tom’s Hardware US. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
Typo: 1-1.4 nm is 10-14 angstrom.Reply
I don’t really understand why so much exponential technical and financial resources are allocated to attempt to maybe gain low performance / power efficiency incremental improvements on a technology, like silicon transistors, that is close to reaching its limit and is a dead end, versus re-allocating those resources to significantly invest in next generation computing technologies like spintronics related technologies (MRAM, Intel MESO concept, French R&D Spintec FESO concept,…) as it seems that could improve power efficiency from 5x to 30x with plenty new opportunities (better suited for AI,…).Reply
The development of CFET is much too expensive compared to opportunities that spintronic related technologies would provide : CFET is unfortunately delaying a much better technology (spintronic technologies).
Also I don’t understand that at this stage DARPA and the US government (US CHIPS Act) still don’t yet make it a top priority fin order that the US regain its technological leadership…