Japan's Rapidus is gearing up to start rivalling for advanced TSMC customers with its 2nm-class process technology sometime in 2027, with some secret sauce involving advanced packaging at the same facility, thus speeding up the production cycle. However, Pat Gelsinger, a former Intel chief executive, says that Rapidus should offer something beyond just streamlined production, something special, according to the Japan Times.
"We applaud the efforts of Japan to bring Rapidus to the market," Gelsinger said at a press conference in Tokyo, responding to a question about the potential of Rapidus, as per Japan Times. "However, we would also say that Rapidus needs some fundamental differentiating technologies, because if they are trying to catch up with a well-executing TSMC without some leap-ahead capabilities, we think that is a very hard road."
One exclusive feature that Rapidus intends to offer compared to other major producers like Samsung, Intel, and TSMC is fully automated packaging integrated within the same site as wafer fabrication, which could shorten production timelines. However, this capability will not be active immediately, since the initial phase of the fab will only include wafer pilot manufacturing without packaging services.
Rapidus is about to start test production of wafers using its 2nm process technology, which relies on gate-all-around transistors and aims to begin high-volume semiconductor manufacturing using this node by 2027. The company aims to deliver the first sample wafers by July and will provide early clients with design tools to help them build prototypes.
Rapidys has set up ASML's EUV and DUV lithography machines inside its Innovative Integration for Manufacturing facility in Chitose, Hokkaido. These systems were installed late last year, and the project has likely achieved the early operational milestone needed to start pilot runs, although neither Rapidus nor ASML has announced the first light-on-wafer milestone.
In addition, Rapidus is establishing a research center, called Rapidus Chiplet Solutions, at Seiko Epson's Chitose location, adjacent to the central facility. Preparations have been underway since October 2024, and equipment installation is scheduled to begin this month. The site will focus on scaling up post-fabrication work, including the development of redistribution layers, 3D packaging processes, assembly design tools, and methods for testing known-good dies (i.e., HBM modules).
Follow Tom's Hardware on Google News to get our up-to-date news, analysis, and reviews in your feeds. Make sure to click the Follow button.
