TSMC's says 1.6nm node to be production ready in late 2026 — roadmap remains on track
No, A16 is not delayed, says TSMC.
TSMC's plans for the next couple of years remain largely unchanged as the company is ready to mass produce chips on its N2 (2nm-class) manufacturing technology starting in late 2025 and A16 (1.6nm-class) fabrication process in late 2026, the company announced at its Open Innovation Platform (OIP) 2024 conference here in Amsterdam, the Netherlands.
"The roadmap you see here is pretty much the same, actually it is the same technology roadmap that I think you saw during the [technology] symposium six months ago," said Dan Kochpatcharin, Head of Design Infrastructure Management at TSMC. "[…] We have N2, N2P, which is coming [to] productions next year and the year after. And then [they are] followed by A16."
The words 'followed' and the slide showing A16 after N2P and N2X was somewhat confusing to me. On the one hand, the slide TSMC shared is very similar to the one it presented back in May. On the other hand, the message sent back then was that A16, N2P, and N2X would be available around the same time, so I asked TSMC's heads of the PR department to clarify.
Indeed, all of these process technologies are slated to be ready for high volume manufacturing (HVM) in late 2026. This is, of course, as far as TSMC would go in official comments, as the company will not pre-announce products for its alpha customer(s) that are set to arrive on the market sometime in 2027. So, let us speculate about the positioning of these manufacturing processes.
Technically, N2, N2P, N2X, and A16 share many similarities: they are all based on nanosheet gate-all-around (GAA) transistors. The N2-series uses super-high-performance metal-insulator-metal (SHPMIM) capacitors to reduce transistor via resistance to improve performance efficiency, whereas A16 uses a backside power delivery network (BSPDN) to improve it even further.
"A16 is basically N2P [with the] the Super Power [Rail], which is our innovative backside power [delivery network]," said Dan Kochpatcharin.
While, generally, a BSPDN enables higher performance and better power efficiency, 'there is no free lunch' here, as noted by Ken Wang, TSMC's Director of Design Solution Exploration. Backside power delivery also adds thermal issues that have to be mitigated. For now, a BSPDN in its current implementation is the best fit for datacenter-grade AI-aimed processors, a market segment that TSMC aims at with its A16 for now.
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As for N2P, it enhances performance over typical N2 without adding complexities associated with a backside power delivery, which is optimal for client devices, such as system-on-chips (SoCs) for smartphones and entry-level PCs. N2X, of course, further enhances performance by adding higher voltages, which might be a benefit for a variety of applications, such as high-performance CPUs.
Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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paviko This is the final confirmation that those names N5, N3, N2 has nothing to do with transitor/gates size. Why Tom's uses 1.6nm in title while it is not even 3nm. Why in every articles Apple SoC is 3nm (N3), when Intel Arrow Lake is 7nm (Intel 4) :DReply -
Sduis
It hasn't meant anything for a long time. None foundry name it. No foundry calls it "Nanometer" or "Angstrom" anymore it's Intel 18A, A16, SF1.4paviko said:This is the final confirmation that those names N5, N3, N2 has nothing to do with transitor/gates size. Why Tom's uses 1.6nm in title while it is not even 3nm. Why in every articles Apple SoC is 3nm (N3), when Intel Arrow Lake is 7nm (Intel 4) :D -
magbarn Meanwhile TSMC took billions of taxpayer dollars for the Arizona foundry that won't even see N3 until 2028. What a bargain!Reply -
igorcd
Arrow Lake is TSMC N3, not Intel 4.paviko said:This is the final confirmation that those names N5, N3, N2 has nothing to do with transitor/gates size. Why Tom's uses 1.6nm in title while it is not even 3nm. Why in every articles Apple SoC is 3nm (N3), when Intel Arrow Lake is 7nm (Intel 4) :D
Intel no longer uses its own nodes. Now TSMC does all chips for Intel (desktop and mobile).
Also Intel 4 was less denser than TSMC/Samsung 5N. For relatively fair naming, it should be Intel '5.5', not Intel 4 -
KraakBal
Crazy amazing what they can do with their hardware, while not going for 15% better node 😱jackt said:2nm is almost ready and amd CPU are still 4nm..... -
stuff and nonesense 2nm is 20 silicon atoms across.. if the node size was actually 2nm and not marketing speak.Reply
Atomic radius empirical: 111 pm
Covalent radius 111 pm
Van der Waals radius 210 pm
While they might scale a little smaller the limit is coming, they will run out of atoms! -
bit_user
They look at density increases from an areal point of view. So, if you start adding more logic layers, it looks higher density even though it's not in 3 dimensions. However, doing things like that will justify continuing to use smaller numbers.stuff and nonesense said:While they might scale a little smaller the limit is coming, they will run out of atoms!
Then, there's the potential for new materials with better electrical performance to enable higher clockspeeds, like I think I recall seeing about graphene or something, a while back. So, I'd be surprised if the treadmill doesn't keep running for at least another decade.
However, what definitely is happening is the amount of improvement from each new node is decreasing, while new node costs are simultaneously going up. So, large dies that can't be sold for exorbitant amounts of money might stay on older nodes, as we're seeing Nvidia do with Blackwell.
I wonder if Nvidia might even drop to a 3 year cadence, for consumer GPUs. If they can't offer compelling improvements after just two...