Toshiba's New STT-MRAM Beats SRAM Power Drain by 90%
Toshiba has developed a new element for MRAM, lowering its overall power consumption.
Toshiba said on Monday that it has developed a prototype memory element for a spin transfer torque magnetoresistive random access memory (STT-MRAM) that (currently) achieves the world's lowest power consumption.
According to the company, the new MRAM element has the potential to surpass the power consumption efficiency of SDRAM as cache memory in practical operations. Toshiba confirmed the performance by using a highly accurate processor simulator, recording a two-thirds reduction in power consumption by a standard mobile chip set carrying out standard operating functions.
"Going forward Toshiba expects to bring the new memory element to STT-MRAM cache memory for mobile processors integrated into smartphones and tablet PCs, and will promote accelerated research and development toward that end," the company said.
Mobile devices like smartphones and tablets depend on high-speed memory to supply the main processor with instructions and frequently requested data. Typically SRAM is used as a cache-memory solution, but improving its performance to match rapidly advancing products has led to increased current leakage in standby mode and during operation, degrading power performance.
Thus, enter MRAM, which is based on magnetic materials. MRAM was introduced as an alternative to SDRAM because it is non-volatile, cutting leak current during standby status. However until now, the drawback to using MRAM was that power consumption exceeded that of SDRAM, making it less ideal for practical applications. The new element developed by Toshiba changes all of that.
"Toshiba's new memory element advances the company's pioneering work in STT-MRAM and overcomes the longstanding operating trade-off by securing improved speed while reducing power consumption by 90 percent," the company said. "The improved structure is based on perpendicular magnetization3 and takes element miniaturization to below 30-nm. Introduction of this newly designed "normally-off" memory circuit with no passes for current to leak into cuts leak current to zero in both operation and standby without any specific power supply management."
Toshiba said it will present three papers on the new STT-MRAM and its technologies on December 11 and 12 at IEDM, the International Electron Device Meeting held by IEEE in San Francisco.