AVA Direct uses Kingston HyperX PC2-8500 1 GB memory modules at 778 MHz Data Rate
Digital Storm uses Corsair Dominator PC2-8500 1 GB memory modules at full speed
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Header Cell - Column 0
Memory Timing
AVA Direct
Digital Storm
Explanation of the Timing
tCL
CAS Latency
5
5
Delay between the CAS signal and the availability of valid data on the data pins (DQ).
tRCD
RAS to CAS Delay
5
5
Delay before a read/write command after bank activation. The cells need to be stabilized by sense amplifiers for proper operation.
tRP
RAS Precharge (Row to Row)
5
5
Time delay needed to close one row access and open a new one.
tRAS
RAS Active to Precharge Delay
15
15
Minimum RAS activation time delay, or the time from the bank activate command until the precharge command can be executed.
CR
Chip Select Issue Delay (Command Rate)
2
2
Time needed between the chip select signal and when commands can be issued to the RAM module IC.
tRRD
RAS to RAS Delay (Between Banks)
3
3
Row to Row delay from one bank to one on another active bank.
tRC
RAS to RAS Delay - Bank Cycle Time (Same Bank)
20
20
Row to Row delay on the same bank. One row discharges and another is activated. (Minimum time of tRAS = tRP).
tWR
Write Recovery Time
5
5
Delay between writes to ensure proper writing to the cells. Ideally, tRAS minus tRCD, to ensure that a premature RAS precharge does not wipe out the data.
tWTR
Write to Read Delay
9
9
The delay to prep the bus for read after a write. (Turn on or off the appropriate I/O buffers, clear existing data, etc.)
tREF
DRAM Auto-Refresh Rate
7.8
7.8
Rate at which the DRAM’s charge is refreshed, in microseconds. Prevents corruption by sending data to sense amplifiers and back to the refreshed cell.
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