JEDEC standards also dictate standard timings for memory modules as well as the other information covered in Table 1. Memory costs hinge on two different key values, while improvements to these values increase the per-unit price.
The first key value is memory latency, which has to do with the delay between initiating a request for memory access (usually by memory location or address) and the time until the data stored at that location is retrieved. Latency is a fundamental measure of memory speed, whereby lower latency means faster memory access.
The other key value also involves latency and is generally referred to as memory timing. Memory timing hinges on four performance metrics, listed as follows in order of importance:
- CAS, usually expanded as column address strobe (or sometimes as column address select), which refers to the column for some physical memory location in an array composed of columns and rows of capacitors used in dynamic random access memory (DRAM) modules (of which all three types of RAM in this guide are sub-types). CAS latency generally appears first in timing sequences for RAM and indicates the number of clock cycles that elapse between when the memory controller instructs the memory module to access a particular column in its current row, and when such access produces the data that resides there.
- Trcd or tRCD, usually expanded as RAS to CAS delay, where RAS is expanded as row address strobe, where R refers to the row for a physical memory location in an array composed of columns and rows of capacitors used for DRAM modules. This value specifies the number of clock cycles between a Row Address Strobe (RAS) and a CAS, and represents the row address to column address delay for a memory module.
- Trp or tRP, usually expanded as RAS precharge, which represents the number of clock cycles required to end access to the current row of memory, and commence access to the next row of memory, so that tRP = time for row precharge.
- tRAS or Tras, usually expanded as RAS access time measured by the number of clock cycles needed to access a certain row of data in DRAM between the initial data request and the precharge command required to commence the next memory access. By definition, tRAS must be greater than or equal to the CAS plus the tRCD, plus an additional two cycles, to leave time for accesses to complete, as they read or write multiple bits of memory, which DDR (2 bits), DDR2 (4 bits), and DDR3 (8 bits) all do in lesser or greater numbers.
RAM memory timings usually appear as sequences of four numbers separated by dashes, as in 5-5-5-15. This indicates that the CAS, tRCD and tRP values are all equal to five clock cycles, and that the tRAS value is equal to 15 clock cycles. The smaller the numbers that appear in these sequences, the tighter memory timings are said to be. Likewise, larger numbers are said to indicate looser timings. Simply put, lower latency costs more, tighter timings cost more and the combination of the two costs the most where memory is concerned.
RAM Value Versus Performance
As we already explained, JEDEC memory specifications set the basis for what kinds of performance and capabilities RAM must deliver. In general, memory that's designed to meet the JEDEC specs but not to exceed them costs the least to design and implement. That's why it's usually the cheapest and is so often used in budget and commercial systems, for which component prices are usually more important than their performance.
Memory vendors usually call this kind of memory "value line memory," where low cost trumps other considerations. This explains why value RAM is drab looking, and generally devoid of heat spreaders, fancy logos and even, advertising coverage. If cost is more important than performance, you should buy value RAM every time. If you plan to add memory modules to your PC, buy value RAM if that's what's already installed, otherwise, match performance as closely as possible if you can't buy exactly the same kind as is already in use.
On the other hand, performance memory is memory that exceeds JEDEC specifications by deliberate design. As any price check will clearly illustrate, performance memory costs more than value memory - sometimes, indeed, a great deal more than value memory of the same type and speed. Most performance memory not only exceeds JEDEC specifications for timings (by making them tighter); it also exceeds JEDEC specifications for speed (by making them run faster than the maximum speeds defined in those documents). Beyond the maximum JEDEC speed for some type of memory, all faster memory is performance memory by definition. In fact, there are those who might be inclined to argue that all DDR3 memory is performance memory because of its relatively high cost. Technically speaking, however, only DDR3-1800 (and the soon-to-be-released DDR3-2000) memory exceeds the defined DDR3 speed range.