Toshiba Intros Low-Power Tech for Embedded SRAM

Toshiba said on Thursday that it has developed an innovative new low-power technology for embedded SDRAM. This tech will be used in smartphones, tablets and other mobile devices to extend the battery life, thus allowing consumers to enjoy more movies, games and other media on a single charge.

According to Toshiba, its new tech actually reduces active and standby power in temperatures ranging from room temperature (RT) to high temperature (HT). This is done by using a bit line power calculator (BLPC) and a digitally controllable retention circuit (DCRC).

"Longer battery life requires lower power consumption in both high performance and low performance modes," the company explains. "As low performance applications require only tens of MHz operation, SRAM temperature remains around RT, where active and leakage power consumptions are comparable. Given this, the key issue is to reduce active and standby power from HT to RT."

Toshiba created a prototype using this new tech which reduced active and standby power consumption at 25°C by 27-percent and 85-percent, respectively. The company explained that the BLPC will predict the power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It then minimizes the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits.

"The DCRC greatly decreases standby power in the retention circuit by periodically activating itself to update the size of the buffer of the retention driver," Toshiba said.

The company introduced the new tech and prototype on Wednesday during the 2013 International Solid-State Circuit Conference in San Francisco, CA. Toshiba didn't say when mobile products would actually begin to incorporate this new tech, but instead said it will continue to develop technologies that contribute to high performance, low power system LSI for mobile products.

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