Researchers Create Transistors for 'Ultimate Scaling' Beyond 10 nm

It has been well established that as transistor sizes continue to decrease, planar technologies are reaching their limit. Thus far, we’ve seen technologies such as FinFET be introduced to partially alleviate this problem.

A team of researchers from the Laboratory for Analysis and Architecture of Systems in France is focusing on a new approach that utilizes a “forest of nanowires all under control of the same gate.” According to IEEE Spectrum, this design is composed of an array of 225 doped-silicon nanowires where each wire has a 14 nm chromium layer surrounding its midsection that serves as the gate.

Promisingly, the design’s manufacturing process doesn’t involve any complicated lithography. The researchers plan to eventually develop IGA nanowires because of their better electron mobility. Though the nanowire forest design is certainly more complex than the aforementioned FinFET transistor design, it could potentially be simplified by reducing the total number of nanowires needed to develop the transistor.

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  • WithoutWeakness
    I know some of these words.
  • cats_Paw
    with transistors so small, how is it that the electricity does not jump from one transistor to another randomly? (i mean, they have to be preaty close to each other, right?
  • tomfreak
    This may sound silly, but I am sticking to the mature technolgy that is just above the 10nm limit then wait a few years for my next upgrade cycle. 2011 socket 14nm/16nm broadwell-E should last 5-10yrs till next upgrade, by then this 'Ultimate Scaling' Beyond 10 nm should be matured enough.