Chicago (IL) - French website Canardplus today published slides that seem to be part of Intel’s IDF presentation program next week and provide some information on the continuation of Intel’s tick-tock strategy until 2012 and 22 nm processors.
According to the slides, Intel does not see any roadblocks in its product strategy which is laid out to deliver new processor architectures in even years and die-shrinks in odd years. Nehalem, scheduled for a Q4 release in desktop flavors, is Intel’s new architecture that will carry the company through 2010.
In 2009, Nehalem will be scaled down from a 45 nm to the 32 nm core Westmere. Sandy Bridge will be the successor of Nehalem’s architecture and debut in 2010 as a 32 nm CPU. Ivy Bridge will shrink Sandy Bridge to 22 nm in 2011 and Haswell will be a completely new architecture that is planned to be introduced in 2012 as a 22 nm chip.
Next week will be packed with technical news about Nehalem, but the published slides do not reveal much more than what we already know - that Nehalem will be an extremely flexible architecture that can be easily fine-tuned because of its modular approach. The number of cores, memory channels, QPI links, cache size, power management features and integration of graphics capability is adjustable and is likely to bring more variety to Intel’s product line-up than ever before. This new capability should make especially Apple happy, as the company tends to always look for differentiators for its products.
Sandy Bridge, will bring some interesting new features. Canardplus speculates that it will have eight cores, 512 kB L2 cache and 16 MB L3 cache. Big changes include the additions of Intel’s "Advanced Vector Extensions", which will bring a switch from 128 bit to 256 bit vectors to increase the floating point performance of the CPUs and extensible new opcode (VEX) to decrease the size of the software code.
Haswell is Intel’s pitch to keep you interested in what is coming down the road and we do not expect Intel to release lots of details of the architecture. What we do know, however, is that it will be a 22 nm chip that in fact may already be part of the research process at Intel’s Oregon D1D fab. Canardplus says that the new architecture will deliver "revolutionary" power savings and will have the capability to support a co-processor such as a vector accelerator within a single package. There is also FMA (Fused Multiply-Add) functionality, which enables multiplication and addition processing via the same instruction and result in much higher compute density.
