Dallas (TX) - Texas Instruments (TI) today announced what the company claims to be the first fully-integrated register and phase-locked loop (PLL) for DDR3 registered dual in-line memory modules (RDIMMs). The chip supports, according to the manufacturer, data rates of 800 to 1066 mega transfers per second (MT/s).
The chip, named SN74SSTE32882, is built in a 130 nm process and wrapped in a 176-pin BGA package. DDR3 memory chips are expected to be manufactured in much smaller structures: Micron, for example, currently samples 78 nm DDR3 memory devices. According to TI, a new approach to integrate PLL, eliminates the need to tune the memory module, which promises to simplify the design and board layout "to accelerate server and RDIMM manufacturers' market entry."
Besides the fact that DDR3 is a natural evolution over current DDR2 memory, the new technology promises lower consumption through a reduced voltage (from 1.8 volts in DDR2 down to 1.5 volts in DDR3), which, however, is expected to disappear with increasing clock speeds. First DDR3 devices are expected to clock in at 800 MHz and consume less power than comparable DDR2-800 modules. Memory clock speed will quickly increase to 1066 and 1333 MHz in 2007 and is likely hit 1600 MHz in 2008/2009.
One of the first platforms taking advantage of DDR3 memory will be Intel's 3-series chipsets, currently code-named "Bearlake", which will be introduced in the second quarter of 2007 as P35 and G33 models. An enthusiast chipset (X38) taking advantage of DDR3 will follow in the third quarter of next year. Micron officials told TG Daily that the company plans to begin mass production of DDR3 memory in the second quarter of next year.
TI's SN74SSTE32882 is sampling today and will be in full production in Q3 2007, TI said.
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