Intel Accidentally Revealed a CPU, Then Pulled it From Public View

Intel CPU
Intel CPU (Image credit: Intel)
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Intel accidentally shared a sneak peek of a next-generation Xeon chip in a promotional video, flaunting the company's advanced packaging technologies. While the chipmaker quickly removed it from the video, we saved a screenshot of the mysterious processor, which poses as a single-die Sierra Forest or Granite Rapids part.

Sierra Forest and Granite Rapids emerged from the shadows at Hot Chips 2023. The processors conform to a tile-based layout, which is an excellent approach toward scalability. The next-generation Xeon chips feature compute chiplets built on the Intel 3 process node and twin I/O chiplets on the older Intel 7 process node. The architectures differ, though. Sierra Forest utilizes Sierra Glen E-cores, whereas Granite Rapids taps into Intel's Redwood Cove P-cores, which power the impending mobile Meteor Lake chips.

Intel

(Image credit: Intel)
Zhiye Liu
News Editor, RAM Reviewer & SSD Technician

Zhiye Liu is a news editor, memory reviewer, and SSD tester at Tom’s Hardware. Although he loves everything that’s hardware, he has a soft spot for CPUs, GPUs, and RAM.

  • derekullo
    Silly Intel!
    With those pictures alone I will start up my own Fab and start mass producing my own chips!
    This will be their greatest blunder!

    ... besides 14nm++++
    Reply
  • JayNor
    "For all we know, Intel can use the same I/O chiplet for Granite Rapids and Sierra Forest."

    Intel has stated that Granite Rapids and Sierra Forest shared the same platform, although they also have said that Sierra Forest would not support above 2S configurations ... which implies there could be some restriction on the number of HSIO lanes used for UPI.
    Reply
  • dalek1234
    578 mm²? That's a bit on the FAT side. What am I missing here? I thought the purpose of chiplets was to produce smaller dies to keep the cost down due to better yields?
    Reply
  • jp7189
    dalek1234 said:
    578 mm²? That's a bit on the FAT side. What am I missing here? I thought the purpose of chiplets was to produce smaller dies to keep the cost down due to better yields?
    ..or to pack a single package with more silicon than the reticle size limit would normally allow.
    Reply
  • PEnns
    I guess using "leaks" each time is getting too obvious....
    Reply
  • kjfatl
    dalek1234 said:
    578 mm²? That's a bit on the FAT side. What am I missing here? I thought the purpose of chiplets was to produce smaller dies to keep the cost down due to better yields?
    It is apparent that this die has many identical cores. Each time a chiplet is halved in size the usable area drops by about 20%. The alternative it to include redundant cores that are unused if they fail test. Even if 20% of the cores have failed, Intel will have a saleable part.
    Reply