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IBM Research Alliance Announces 5nm GAAFET Chip With 40% Performance Increase Over 10nm FinFET Chips

IBM, Samsung, Global Foundries, and other equipment suppliers from the IBM Research Alliance announced the development of the first 5nm chip using a gate-all-around FET structure. The news comes two years after the alliance announced the development of the world’s first 7nm chips, which should enter production next year.

Samsung recently revealed that it plans to develop a 4nm GAAFET chip, too, but we don’t know yet when it’s going to be available.

World’s First 5nm Chip

Although Moore’s Law seems to have slowed down quite a bit in the past few years, IBM and its partners were able to push it forward using new chip manufacturing technologies such as extreme ultraviolet (EUV) lithography, nanosheet transistors, and gate-all-around FET structures.

All of these combined seem to have made it possible to develop 5nm chips that are ready for mass production. Not only that, but the 5nm chips also promise a 40% increase in performance or a 75% reduction in power consumption over the 10nm process technology currently in use by Samsung. Even though we may not see such 5nm chips on the market until 2021 or later, the improvement still looks significant.

IBM also said that a 5nm chip could be made out of 30 billion transistors, a 50% increase from the 20 billion transistors the company announced for its 7nm chip two years ago.

GAAFET And EUV

According to IBM, the EUV lithography can enable continuous adjustment for the width of the nanosheet transistor architecture, all within a single manufacturing process or chip design. This permits the fine-tuning of performance and power for specific circuits, which is not possible with today’s FinFET transistor architecture that is limited by its current-carrying fin height.

Although FinFET processes can also be scaled down to 5nm, reducing the space between the fins doesn’t increase the current flow for additional performance.

“Today’s announcement continues the public-private model collaboration with IBM that is energizing SUNY-Polytechnic’s, Albany’s, and New York State’s leadership and innovation in developing next generation technologies,” said Dr. Bahgat Sammakia, Interim President, SUNY Polytechnic Institute. “We believe that enabling the first 5nm transistor is a significant milestone for the entire semiconductor industry as we continue to push beyond the limitations of our current capabilities. SUNY Poly’s partnership with IBM and Empire State Development is a perfect example of how Industry, Government and Academia can successfully collaborate and have a broad and positive impact on society,” he added.

IBM also believes that the 5nm process will enable another big leap in performance, not just for regular consumer devices, but also for next-generation machine learning chips and supercomputers. More details about its 5nm process will be revealed at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto, Japan, which is happening this week.