Samsung Reveals 4nm Process Generation, Full Foundry Roadmap

Kinam Kim, President of Samsung Electronics’ Semiconductor BusinessKinam Kim, President of Samsung Electronics’ Semiconductor BusinessAt the annual Samsung Foundry Forum, Samsung announced its foundry’s roadmap for the next few years, which includes an 18nm FD-SOI generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.

18nm Fully Depleted – Silicon on Insulator (FD-SOI)

Samsung will expand its 28FDS process into a broader platform that will also offer Radio Frequency (RF) and embedded Magnetic Random Access Memory (eMRAM) options to its foundry customers.

The company will also launch the 18FDS process, which is the next-generation process that targets low-cost IoT chips.

8nm Low Power Plus (8LPP)

The 8nm process generation seems to be Samsung’s last generation before the company plans to use extreme ultraviolet (EUV) lithography. The company said that the 8LPP process combines key process innovations from its 10LPP process, as well as further improvements in performance and gate density compared to 10LPP.

7nm Low Power Plus (7LPP)

The 7LPP process will be Samsung’s first generation to use EUV lithography. According to the company, EUV lithography is what will allow Moore’s Law to continue and foundries to keep shrinking transistors down to 1nm.

6nm Low Power Plus (6LPP)

The 6LPP generation will improve on 7LPP, primarily by allowing greater area scalability and making chips more efficient.

5nm Low Power Plus (5LPP)

The 5LPP process will be Samsung’s last one to use a “FinFET” structure, as that type of architecture reaches its physical limits. This generation will also focus on area reduction and lower power consumption for chips.

4nm Low Power Plus (4LPP)

The 4LPP process generation will be Samsung’s first to use a “Gate All Around FET” (GAAFET) transistor structure, with Samsung’s own implementation dubbed “Multi Bridge Channel FET” (MBCFET). The technology uses a “Nanosheet” device to overcome the physical limitations of the FinFET architecture.

Pushing Moore’s Law Forward

Even though process generations may not accurately describe how small the transistors actually are these days, all major chip fabrication companies, including Intel, Samsung, Global Foundries, and TSMC, seem to be pushing Moore’s Law to its very limits and making steady progress with each process generation.

Samsung’s transition to EUV lithography and GAA FETs in the near future should lead to faster and more efficient chips in our devices for the foreseeable future. The competition is likely not far behind, or may even be ahead, but they may also be less willing to share information years ahead of production.

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  • AgentLozen
    Intel has made me cynical towards smaller processing nodes in the last few years.

    "February 3, 2018"
    Intel Announces Next Generation Processors

    In a press conference today Intel has announced that it's next generation "Alien Lake" processors will soon be available for purchase.

    Intel has described Alien Lake as a dramatic improvement over last generation Kaby Lake processors. An Intel spokesperson had this to say about the new architecture,
    Intel said:
    "A team of Intel excavators discovered an alien space ship crash site over 10 years ago. Our best scientists and engineers have been reverse engineering the technology we found and have built the Alien Lake cpus around it. We have achieved performance beyond our wildest expectations. Expect Alien Lake to revolutionize how the world views computing."

    Intel has indicated that Alien Lake will be built around a sub-1nm process and is at least 40 years more advanced than any if its competition. Stay tuned to Tomshardware for our full review of Alien Lake."

    Then, a week later, the reviews show a +3% increase to IPC and a 0% increase to clock speed over Kaby Lake. However, it DOES use 10% less power. So there's that....

    It's been this way since Ivy Bridge and I'm now convinced that die shrinks offer no perceivable improvements over their larger counterparts.
  • InvalidError
    496490 said:
    It's been this way since Ivy Bridge and I'm now convinced that die shrinks offer no perceivable improvements over their larger counterparts.

    Die shrinks still enable chip designers to pack more transistors in the same power and area budget. Intel simply chose to apply most of those gains to increased IGP performance and smaller die sizes instead of increasing core count. Now that AMD has been reasonably successful with Ryzen, you can expect more aggressive movement from Intel over the next few years.
  • anbello262
    496490 said:
    Then, a week later, the reviews show a +3% increase to IPC and a 0% increase to clock speed over Kaby Lake. However, it DOES use 10% less power. So there's that.... It's been this way since Ivy Bridge and I'm now convinced that die shrinks offer no perceivable improvements over their larger counterparts.


    That is only valid for desktop processors. For GPUs, mobile systems, NAND, XPoint and a lot of other stuff, this things are GREAT. Smarthpones are advancing a lot every year, and we're not very far from the moment a high end smartphone equals a lowish-tier desktop, and high end ultrathin/ultralight laptops have no more heat issues. This will help enable that.

    For desktop processors, on the other had, die shrinks usually mean harder to cool processors that consume less energy, which balances out and we get a refreshed last generation'.