The motivation of this move is based on the fact that an increased number of CMOS transistors in 3D stacking will create an environment in which there will not be enough C4s even for single-die processors with single-surface power delivery.
IBM submitted a patent application that describes an integrated power architecture and distribution between a processor layer that is "coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices."
The company stressed that this specific application only relates to power delivery, but there was the notion that this approach could also be used as a future data path as the described C4 layer "provides power to high-speed signaling" and the "I/O layer provides connectivity for signaling between [the] high-performance high-power processor layer [and] I/O layer in a reverse fashion similar to the […] description for power delivery from one layer to another layer."