Today on our desktop computers, we have CPUs with core counts that we can count through with our fingers. Intel, however, has just presented at SC'11 its the first silicon of the "Knights Corner" co-processor that is capable of delivering more than 1 TFLOPs of double precision floating point performance.
Such power of Intel's MIC (many integrated core) architecture won't be used to play Crysis, but rather it'll be put towards highly parallel applications, such as weather modelling, tomography, proteins folding and advanced materials simulation.
"Intel first demonstrated a Teraflop supercomputer utilizing 9,680 Intel Pentium Pro Processors in 1997 as part of Sandia Lab's 'ASCI RED' system," said Rajeeb Hazra, general manager of Technical Computing, Intel Datacenter and Connected Systems Group. "Having this performance now in a single chip based on Intel MIC architecture is a milestone that will once again be etched into HPC history."
Knights Corner, the first commercial Intel MIC architecture product, will be manufactured using Intel’s latest 3-D Tri-Gate 22nm transistor process and will feature more than 50 cores. Furthermore, Intel promises compatibility with existing x86 programming model and tools.
Hazra boasted that the Knights Corner co-processor is unlike traditional accelerators in that "it is fully accessible and programmable like fully functional HPC compute node, visible to applications as though it was a computer that runs its own Linux-based operating system independent of the host OS."
Intel says that its MIC architecture benefits from the ability to run existing applications without the need to port the code to a new programming environment. Intel believe that this will allow scientists to use both CPU and co-processor performance simultaneously with existing x86 based applications without needing to rewrite them to alternative proprietary languages.
And Knights Corner isn't serving the same market as Interlagos, so they're not really directly comparable.
You know what this is?
I think this is Intel's answer to ARM's server bids.
Think about it.
50+ cores at 1.2 GHz? That sounds a lot like what ARM will be promising in the near future.
Except that everyone who wants to go the low-power route needs to re-write their programs for the ARM instruction set. With this they don't have to. The tools for Xeon optimization are also the same.
So you can have a powerful 4/6/8/10-core Xeon processor (that you probably already own) but bolting this on, combined with Intel's advancements in power consumption (Sandy Bridge is already very good on idle battery life in notebooks), should make a changeover to ARM technology a hard sell.