Intel has published a patch (discovered by Phoronix) that enables support for its Intel Software Defined Silicon (SDSi) mechanism in Linux. The technology is meant for upcoming Intel Xeon processors and is designed to activate additional silicon features after a processor has been deployed.
The patch does not mention any specific features it is meant to unlock or any specific Xeon Scalable processors it is meant to upgrade (we think Sapphire Rapids), yet it gives some general understanding how it is supposed to work. As it turns out, the whole process is purely software, so it does not require any manipulations with hardware. Therefore, it can be done relatively easily.
Intel's SDSi initiative seems to be a major one, yet Intel is not new to offering software upgrades to its CPUs. The most recent example of such software upgradeability is Intel's Virtual RAID on CPU (Intel VROC) technology that relies on the Intel Volume Management Device (VMD) hardware built into the CPU and has to be activated using a special hardware key. The company also once offered its Upgrade Service software upgrade capability for its entry-level client CPUs that would increase their clock speed, unlock a previously unused portion of cache, and activate Hyper-Threading technology.
Intel yet has to fully describe what it intends to offer under its Software Defined Silicon initiative, but the number of possible options is quite limitless.
Originally, Intel's Pentium II/III/4 Xeon processors were essentially desktop parts with additional cache and SMP (symmetrical multiprocessing) support. But Intel's Xeon processors have gained quite a lot of functionality in the last 15 years that is not supported by client CPUs and is not required by client systems. In fact, Intel's latest Xeon Scalable CPUs support instructions that are not supported by client models.
In more recent years, Intel began to differentiate features and performance of its Xeon Scalable processors with premium parts supporting more memory, eight-way SMP capability, the highest number of cores, and all technologies that the chip giant has to offer.
With the launch of its 4th Generation Xeon Scalable 'Sapphire Rapids' processors, Intel will bring support for plethora of new instructions and special-purpose accelerators designed for emerging workloads. Yet, many of Intel's enterprise customers that use on-premise servers may not see any immediate value in technologies like Advanced Matrix Extensions (AMX), Data Streaming Accelerator (DSA), or CXL 1.1. In fact, even hyperscale cloud service providers may not need all the features on all of their systems.
To meet the immediate needs of its clientele, Intel wants to offer them CPUs in the configurations they need now, but with SDSi it can leave the door open for future software upgrades should a client need additional functionality or just decides to repurpose a machine. Such upgradability ensures that Intel's clients do not go to AMD if they need an extra feature or two and will still pay Intel for its technologies.
Here is the official description of Intel's Software Defined Silicon (SDSi) mechanism:
Intel Software Defined Silicon (SDSi) is a post manufacturing mechanism for activating additional silicon features. Features are enabled through a license activation process. The SDSi driver provides a per socket, ioctl interface for applications to perform three main provisioning functions:
1. Provision an Authentication Key Certificate (AKC), a key written to internal NVRAM that is used to authenticate a capability specific activation payload.
2. Provision a Capability Activation Payload (CAP), a token authenticated using the AKC and applied to the CPU configuration to activate a new feature.
3. Read the SDSi State Certificate, containing the CPU configuration state.
The ioctl operations perform function specific mailbox commands that forward the requests to SDSi hardware to perform authentication of the payloads and enable the silicon configuration (to be made available after power cycling).
The SDSi device itself is enumerated as a PCIe VSEC capability on the Intel Out Of Band Management Services Module (OOBMSM) device. The SDSi device is a cell of the intel_pmt MFD driver and as such has a build dependency on CONFIG_MFD_INTEL_PMT.
Not really. If this can help to lower the price of the CPU is a good thing. Not everyone needs every single feature that is available in the CPU. I am ok with them to even lower the number of PCIE lanes etc if this means lower cost. Features like AMX and DSA etc... not everyone needs them. These are also optional features that are added into CPU.
But it wouldn't help to lower the price. It ensures that every single buyer will have to pay for fully functional hardware, that then gets software locked. The cost to produce the CPU does not go down, therefore the minimum price cannot go down. It just adds extra profit from users who would have previously had those features by default.
I remember Intel tried something like this in laptops. You would but a gimped budget PC, then get a popup along the lines of "pay us $100 to download a better CPU", which would unlock your CPU to run at the full clock rate that it was built for.
As I recall, it was a PR nightmare for Intel that they had to backtrack on immediately.
" Such upgradability ensures that Intel's clients do not go to AMD if they need an extra feature or two and will still pay Intel for its technologies. "
I would argue that this scheme guarantees that their clients go to AMD, and never look back.
I understand why Intel would think they could get away with this when they had a monopoly on server CPUs. But it's weird for them to pull this stunt when they're behind on tech and losing customers en masse.
Well, Brian Krzanich recently returned the Intel. Maybe it was always his bad idea.
To quote TH's Paul Acorn from an article last year:
Intel needs to start taking a page out of AMD's book and do the same before AMD eats up a large chunk of Intel's share, and drop these stupid ideas to monetize everything like it's a mobile game...
I don't understand this mentality at all.
Very very few customers buy the top-of-the-line CPU in any market. Every Xeon starts life as the best-of-the-best, but Intel makes more top-end silicon than there are customers to purchase it. So they cut down on features and clock speeds to make cheaper chips that fill the majority of the market. Same with Extreme Edition CPUs. Every CPU starts out as an Extreme Edition and then is cut down to the bin it needs to be sold.
At least with this scheme you can pay to unlock features and power later that you couldn't afford at initial purchase time instead of these features being perma-disabled via laser-slicing off circuitry.
Because that's really what you're arguing here. "I want my disabled features to STAY disabled!"
If graphic card manufacturers can sell at a premium based on FP64 and driver capability, so can they.
Consumers are now willing to tolerate a lot more than they did. Remember when something as simple as processor serial number caused so much outcry back in PIII days?
That means don't build that feature into the silicon and artificially lock it behind a software lock.
Either give the customer access to the entire silicon, or don't put the stupid feature into the silicon.
If that means making more waffer masks to segment your product, that's a Intel specific problem, not a customer problem.
Intel is the one that loves nickle & diming the customer.
The customer hates that kind of behavior.