Update 12/11/2010 7:40am PT: Intel tells us that the roadmap ASML presented at the IEDM conference (cited in our coverage below) was altered by ASML and doesn't accurately reflect Intel's public roadmap. Intel's version of the roadmap, which we're presenting below, does not have node naming conventions listed beyond 10nm+ and is "meant to be read more generally." We've included Intel's public roadmap immediately below, and ASML's version of the roadmap follows.
An Intel process technology roadmap has surfaced (reported by WikiChip) that sees Intel introducing a new process every two years for the next decade, resulting in the 1.4nm node in 2029. There will also be two additional intra-node optimizations per node, with a 10nm+++ in 2021.
The roadmap was shown in an ASML presentation at the ongoing IEDM 2019 conference and it dates back to a September Intel presentation. It shows 10nm in 2019, 7nm in 2021 and 5nm in 2023, respectively in development and in definition. In October, Intel announced its intention to move back to a two to two and a half year cadence and stated its confidence in 5nm.
The roadmap then reveals that Intel has 3nm and 2nm in pathfinding and 1.4nm in research. It is the first time Intel has disclosed that it is working on those nodes. The timespan between all nodes is roughly two years, placing 3nm in 2029. However, since 7nm is slated to launch in the fourth quarter of 2021, any small delay in the next decade would let 3nm slip into 2030 or beyond.
The roadmap does not reveal any details about Intel’s process technology plans, other than saying that each node would be the optimal cost-performance path and introduce new features. For 7nm, that means the insertion of EUV. For 5nm, it is expected that Intel will move from tri-gate FinFETs to gate-all-around nanowires, possibly followed by stacked nanowires at later nodes. Intel is likely also aiming to use next-generation high-NA EUV lithography at 5nm: Intel's lithography director recently held "a call to action to keep high-NA EUV on track" for its 2023 schedule, according to SemiEngineering.
As Intel announced at its investor meeting this year, the company will continue the practice it started at 14nm to introduce intra-node process optimizations (denoted as '+' revision), which are described as the easiest design path. (Except for 10nm, where 10nm++ leads to 7nm in the slide instead of 10nm.)
Interestingly, at the 10nm node, the roadmap shows a path towards a ++ and a +++ version, instead of the expected 10nm+ and 10nm++. It is unclear if Intel has renamed the nodes that were previously announced as 10nm+ and 10nm++, or if Intel has developed a fourth variant of 10nm. The EUV sign above 2021 could indicate that 10nm+++ leverages EUV.
Lastly, every node shows a back port opportunity to the previous node’s ++ version. This could either refer to the back porting of new processes' features to old processes, or alternatively, back porting full chips to the previous node. Intel disclosed a year ago that it would be more flexible with what nodes its IP could be manufactured on, as it admitted that its 10nm IP was bottlenecked by the process' delay.
The roadmap does not show if 10nm too has the option for a backport.
If Intel’s process roadmap holds true, then Moore’s Law will live on for at least another decade, rendering the increasing reports of its ending false for at least another decade. A 1.4nm node might have a density of 1.6 billion transistors per square millimeter. Although end products often have a density lower than theoretically possible, such a density would have let Intel fit as many transistors in a single square millimeter as there were in 2014's Broadwell 14nm lead product.
More realistically, though, the roadmap presents an optimistic schedule after the hiccups Intel had at 14nm and 10nm. A similar long term roadmap early this decade had shown 7nm as being scheduled for 2017. On the other hand, a full decade roadmap presents a bold sign that Intel is still serious about leading edge process technology and has confidence in Moore's Law.
This sentiment was echoed a few months ago by Intel's Jim Keller, who proposed a 50x scaling path that included feature size reduction, the introduction of stacked nanowires and 3D stacking.
Separately, at an investor conference today, Intel chief engineering officer Murthy reiterated that 5nm is well into development and on track for 2023. He also said that Intel intends to introduce a “full portfolio” of 7nm products within a year of its lead product. More closely, he stated that Tiger Lake would launch "in the early part" of next year.