EDIT: The text has been adjusted to reflect that the chip was tested in a server platform.
A leaked Intel CPU has been discovered on the SiSoft database (opens in new tab). This CPU has six cores, Hyper-Threading, and was used in a server or workstation configuration with another identical six-core for a total of 12 cores and 24 threads. What's interesting, however, is that the amount of L2 cache per core has been increased from just 256 KB on Coffee Lake CPUs, like the Core i9-9900K, to 1.25 MB. This is even more cache per core than offered by the Core i9-10980XE (1 MB) and Ice Lake mobile CPUs (512 KB).
The amount of L2 cache per core is important to note because it has a big architectural impact on performance. This difference might be between two totally different architectures (AMD's Bulldozer vs. Zen), or between two architectures that share the same core but almost nothing else (Intel's Skylake vs. Skylake X). This CPU is very likely using one of Intel's new architectures designed for the 10nm node. But which architecture is used?
The most likely possibilities are that either this is a 10nm Ice Lake, Tiger Lake, or a 14nm Rocket Lake processor. There is little information on the latter two architectures, but one Tiger Lake leak revealed it has 1.25 MB of L2 cache per core (opens in new tab), just like this leaked CPU. That might be evidence that this is actually based on Tiger lake, but there has been no indication thus far that Tiger Lake will offer more than four cores, while Rocket Lake has been seen with eight cores (opens in new tab). This leaked CPU also has less L3 cache than the leaked Tiger Lake CPU; because L3 caches can be quite large, it makes sense that a CPU on a less-dense node would have less L3 cache than a CPU on a denser node.
Intel has already revealed it has the option of backporting architectures intended for 7nm onto the 10nm node (opens in new tab), so the possibility of Rocket Lake being a 14nm architecture with designs intended for 10nm CPUs is certainly there.
Given that the chips were tested in a server, that opens up the possibility that the chip is simply Ice Lake for server, which would have more L2 cache per core than Ice Lake for mobile (see Skylake vs. Skylake X).
Overall, it's hard to make any firm conclusions based on this result. The possibilities are many and the evidence is very thin. The one certainty is that this CPU is not a Skylake derivative. What isn't certain is whether or not this is 14nm Rocket Lake with a backported core, 10nm Tiger Lake, or something totally different, like Ice Lake for server.
I think Intel would be wise to increase Cache per core. AMD has done this with zen+ to Zen2 and i suppose it is part of the reason Zen 2 is suck a great architecture.
Things are going to be pretty interesting for a while. With AMD firing on all cylinders and Intel finally waking up from the Sandy Bridge slumber it is going to be a great next few years for consumers.
That makes absolutely no sense.
I thought the exact same thing.
Moore's Law is about the speed of increasing the number of transistors on an IC over time. He assumed transistor count would double every 18 months or so. So... yeah. You didn't make much sense there.
As for keeping performance on top, they are failing at that right now. All they really have at this point is gaming. Mostly just because Intel maintains a clock speed advantage, because of how good they have gotten at 14nm production, but they are falling behind sorely in programs that can use more cores. On top of that most games don't take advantage of all the cores modern CPUs have to offer so there is really only that keeping Intel on top as fewer faster cores is what they are doing... but they are losing even that advantage.
All the way down to 4 cores.
Anyway, the critical clue that it's a server CPU (besides the huge L2 cache) is the dual-CPU configuration. They don't support that on any CPUs besides the server range (which sometimes do find their way into "workstation"-branded chassis, it should b enoted).
In my opinion, the only reason for all the speculation is just to milk a longer article out of this one tiny leak.
Right now there's nothing obvious about it. This could be anything from a more modified Cooper Lake (than anticipated) to Ice Lake to an early Sapphire Rapids sample.
The only conclusion for a different architecture is the larger L2, but they could keep the current arch/core-design and only adjust the caches (like they're currently doing with Tiger Lake/Willow Cove).
Also the smaller L3 is no certain hint for a low-density 14nm process. Maybe the larger L2 allows for a smaller L3 as a reasonable trade off ... who knows and it is still a 10nm process? A lot of speculation ... at least it seems to be a Xeon die, because I do not remember dual socket support for anything else ... or maybe SiSoft identification was wrong and it was no dual-socket, but a MCM-design instead ... just wait and see ...
Also, I wouldn't think they'd increase it, due to the fact that it's still made on 14 nm, but I can't rule it out.
And no freaking way would it be Sapphire Rapids, this far out. That's insane. If they would already have Sapphire Rapids samples that can boot and run benchmarks, then I doubt they'd even bother with Cooper Lake.
The thing is that the article didn't even mention Cooper Lake. Instead, just rehashing a bunch of stuff that clearly wasn't relevant, when you consider that none of the desktop or workstation chips support dual-CPU configurations.
That was my main point. No, there's absolutely no multi-CPU support outside of their server (meaning LGA 3647, 4189, or 4677) sockets. LGA 2066 can't do it, and certainly not their desktop sockets.
2x6 would be weird, but I guess not an implausible move for a desktop-class CPU.
Gemini Lake also added a 4th execution port, so the performance improvement wasn't just due to more cache.