TSMC Announces N4P Process, a Refined N4 Chip Node

(Image credit: TSMC)

TSMC today announced a refinement of its N4 manufacturing process. Termed N4P, the new node brings about tangible Power/Performance/Area improvements over N4, bringing another manufacturing option to TSMC's cadre of clients. The technology joins TSMC's staple of offerings, covering many N - the company has nodes on N5, N4, N3, and now N4P technologies. First tape-outs on N4P are expected to materialize by the second half of 2022.

TSMC quotes that N4P further improves N4's performance by around 6%. While this is likely not significant enough for any prospective client to scale from N4 to N4P, it is more interesting for clients on less modern fabrication nodes (even N5) to rake in more benefits than by going N4. At the same time, this creates an interesting cadence of clients for TSMC. Companies rarely rearchitect or develop their designs for every successive manufacturing node. Nowadays, taping out a new chip for a new node means an investment to the tune of hundreds of millions of dollars, meaning that TSMC now has more nodes through which to distribute their clients than if it were scaling vertically.

TSMC does say that N4P will bring tangible improvements over N5, though, and they provide more data for that comparison than against N4, which is limited to performance estimates. For example, compared to N5, N4P will deliver an 11% performance boost, a 22% improvement in power efficiency, and a 6% improvement in transistor density. Importantly for customers, TSMC says that N4P features a simplified (and cheaper) manufacturing process, requiring fewer masks and less wafer turnaround time. Additionally, TSMC says it sought to maximize design compatibility between N4 and N5, reducing the cost of completely porting designs over to a new node.

"With N4P, TSMC strengthens our portfolio of advanced logic semiconductor technologies, each with its unique blend of performance, power efficiency and cost. N4P was optimized to provide a further enhanced advanced technology platform for both HPC and mobile applications," said Dr. Kevin Zhang, Senior Vice President of Business Development at TSMC. "Between all the variants of N5, N4 and N3 technologies, our customers will have the ultimate flexibility and unmatched choice of the best mix of attributes for their products."

Francisco Pires
Freelance News Writer

Francisco Pires is a freelance news writer for Tom's Hardware with a soft side for quantum computing.