Taiwan Semiconductor Manufacturing Co. has started risk production of chips using its N3 (3 nm-class) fabrication process, two reports from Taiwan read. As usual, it will take the contract maker of chips and its partners several quarters to polish off the technology and designs before both enter high-volume manufacturing (HVM).
TSMC initiated pilot production of N3 chips at its Fab 18 at the Southern Taiwan Science Park near Tainan, according to reports from DigiTimes and TechTaiwan. HVM of chips using the new node will commence in the second half of the year, but since cycle time for the new process is over 100 days, the first N3 chips made by TSMC will ship in early 2023.
TSMC's N3 fabrication technology is the foundry's next-generation node that was designed for both smartphones and high-performance computing (HPC) applications, a departure from TSMC's usual tactics to address mobile designs first. The new process will aggressively use extreme ultraviolet lithography (EUVL) for 'over 20 layers' and deliver substantial improvements over existing N5-bases nodes. TSMC promises a 10% to 15% performance gain (at the same power and transistor count), up to 30% power reduction (at the same clocks and complexity), up to 70% logic density gain, and an up to 20% SRAM density gain.
It is rumored that the first customers to adopt TSMC's N3 technology will be Apple and Intel, though it is unclear what exactly will these companies make using the new technology.
Other chip designers may wait for TSMC to introduce its N3E, an extended version of N3, before jumping on the 3 nm bandwagon. N3E is said to feature an improved process window, which is a wider choice of manufacturing parameters to achieve good yields along with performance enhancements and lower power. Meanwhile, N3E will only be available in late 2023 or early 2024.
