Intel Core Ultra 200 CPU specs allegedly leaked — Arrow Lake tops out at 24 cores and 5.7 GHz boost clock at 250W
Arrow Lake-S specs have reportedly been finalized.
The specifications for Intel's upcoming Core Ultra 200 (codenamed Arrow Lake) series, which will rival the best CPUs, have purportedly been finalized. Benchlife has released a full table of the alleged specifications featuring all five SKUs arriving later this year. Intel's initial batch of SKUs that will come with Arrow Lake's debut will be the Core Ultra 9 285K, Core Ultra 7 265K, Core Ultra 7 265KF, Core Ultra 5 245K, and Core Ultra 5 245KF.
Core Ultra 9 285K is the flagship chip with eight P-cores, 16 E-cores, 36MB of L3 cache, and a maximum turbo frequency of 5.7 GHz courtesy of Intel's Turbo Velocity Boost technology. Base power is rated at 125W, and the maximum turbo boost power limit is set at 250W.
Unlike the Core i9-14900K, Intel keeps the same core count configuration, featuring a 2:1 ratio for the P and E-cores. Clock speed is taking a noticeable step down; however, with the 285K "only" achieving 5.7 GHz, there is a 300 MHz decline compared to the 14900K. This is a result of Intel switching to a new process node and architecture. L3 cache is the same between both chips, but the Core Ultra 9 chip has 8MB more L2 cache.
The Core Ultra 7 265K/KF drops the core count to 8 P-cores and 12 E-cores, featuring a maximum turbo clock of 5.5 GHz. The cache also drops to 30MB of L3 and 36MB of total L2 cache. Power metrics remain the same as the 285K at 125W and 250W, respectively. The new Ultra 7 parts feature the exact core count as their Core i7 predecessors and a similar boost clock featuring a TVB clock just 100 MHz shy of the Core i7-14700K/KF. The Ultra 7 parts also have more cache, featuring 3MB more L3 and 8MB more L2.
Header Cell - Column 0 | Core Ultra 9 285K | Core Ultra 7 265K / KF | Core Ultra 5 245K / KF |
---|---|---|---|
Cores / Threads | 8+16 / 24 | 8+12 / 24 | 6+8 / 14 |
L3 Cache / Total L2 Cache | 36MB / 40MB | 30MB / 36MB | 24MB / 26MB |
Thermal Velocity Boost | 5.7 GHz | 5.5 GHz | 5.2 GHz |
Turbo Boost Max (TBMT 3.0) | 5.6 GHz | 5.5 GHz | None |
P-Cores Peak Boost | 5.6 GHz | 5.4 GHz | 5.2 GHz |
E-Cores Peak Boost | 4.6 GHz | 4.6 GHz | 4.6 GHz |
P-Cores Base Clock | 3.7 GHz | 3.9 GHz | 4.2 GHz |
E-Cores Base Clock | 3.2 GHz | 3.3 GHz | 3.6 GHz |
CPU Base Power | 125W | 125W | 125W |
Maximum Power | 250W | 250W | 159W |
The Core Ultra 5 245K/KF features six P-cores and eight E-cores accompanied by 24MB of L3 cache and 26MB of L2 cache. Compared to the Ultra 7 and 9 parts, core clocks take a big hit, peaking at just 5.2 GHz for the maximum TVB turbo clock. There is also a complete lack of IBMT 3.0 support, which could affect performance in some scenarios.
Clocks are very similar, and core counts are identical compared to the Core i5-14600K/KF. The Ultra 5 parts are just 100 MHz slower than the 14600K/KF SKUs when it comes to maximum turbo boost clock speeds. The Arrow Lake parts also have improved cache, featuring the same amount of L3 cache as the Raptor Lake Refresh counterparts but six megabytes more L2 cache.
Overall, specs aren't massively changing compared to the Raptor Lake CPUs Intel has today. The significant tidbits that are changing are the process node and architecture, which are entirely new for this generation. The Core Ultra 200 series will take advantage of the Arrow Lake architecture, which features new Lion Cove P-cores that feature hyperthreading. Intel will also take advantage of third-party silicon again, ditching its homebrewed 18A process node for a competing design from TSMC.
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Aaron Klotz is a contributing writer for Tom’s Hardware, covering news related to computer hardware such as CPUs, and graphics cards.
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Eximo "Unlike the Core i9-14900K, Intel keeps the same core count configuration, featuring a 2:1 ratio for the P and E-cores."Reply
That doesn't make any sense. Both are 8P + 16E configurations. Unless you are talking about hyperthreading for something.
Also wouldn't it be 1:2 P to E cores? -
thestryker If the performance in gaming can top X3D parts I'll certainly be onboard with one of the top two SKUs. I know there's no such thing as a perfect CPU, but I'd like to have top tier gaming performance to go with top tier MT.Reply
Intel will also take advantage of third-party silicon again, ditching its homebrewed 18A process node for a competing design from TSMC.
A) It would be 20A
B) We actually don't know what the K SKU manufacturing process is for sure because Intel has been extremely lacking in details. It's not impossible that the Compute Tile on the K SKUs is 20A and none of the undoubtedly many forthcoming lower SKUs/mobile parts are. -
Jame5 I must have missed something somewhere along the way. Is this the first CPU design with more L2 cache than L3 cache? I always thought that L3 > L2 > L1 caches are pretty much by design. each level of cache is larger than the previous, but also slower.Reply -
joeer77 This is Intel 1278 gate all around chip. Incorporating backside power deliver and EUV as well. A radical departure from 1276 FinFET. If it's only 18% faster at best I am going to be disappointed.Reply -
thestryker
There are technically 4 tiers if cache in this architecture, but the main benefit for L3 has been that it's shared among the cores. So while there is more L2 than L3 everything below L3 isn't shared (for the P-cores, I don't remember if Skymont E-cores share L2 for the 4 core clusters like the predecessors).Jame5 said:I must have missed something somewhere along the way. Is this the first CPU design with more L2 cache than L3 cache? I always thought that L3 > L2 > L1 caches are pretty much by design. each level of cache is larger than the previous, but also slower. -
TheSecondPower
The Skymont LPE cores in Lunar Lake do share a 4 MB L2 cache.thestryker said:I don't remember if Skymont E-cores share L2 for the 4 core clusters like the predecessors -
TheSecondPower
The Snapdragon X Elite has 36 MB of L2 in 12 MB blocks or 3 MB per core, but only 6 MB of L3.Jame5 said:I must have missed something somewhere along the way. Is this the first CPU design with more L2 cache than L3 cache? I always thought that L3 > L2 > L1 caches are pretty much by design. each level of cache is larger than the previous, but also slower.
https://www.anandtech.com/show/21445/qualcomm-snapdragon-x-architecture-deep-dive/2 -
YSCCC Don’t looks like it will have significant performance increase from RPL, and will be interesting to see if the similar power budget will cook it alsoReply -
ingtar33 if these are going to be more cpus pulling in 400W of peak power i don't know how anyone would risk buying one after the disaster with 13th and 14th gen cooking themselves.Reply