Overindulge Yourself with QX6800

Features
By published

System Settings

So how do these guys get their systems humming? The charts below will give you tweakers and overclockers some ideas on what they do to get the performance that both system builders guarantee.

Frequencies And Voltages

Swipe to scroll horizontally
SettingFalcon-NWBiohazardUnits / Explanation
CPU Frequency3.733.50GHz
CPU Multiplier11X12XTimes faster than the system clock
FSB (Effective Frequency)13471167MHz
Ratio of Memory to FSBUnlinked1:1Unlinked = Asynchronous operation
Memory Frequency10661167MHz (effective frequency)
SLI-Ready MemoryEnabledDisabledIncreased drive strengths on certain timings and settings
Graphics Core Frequency626648MHz
Graphics Memory Frequency10001000MHz
CPU Core Voltage1.65001.4875Volts
CPU FSB Voltage1.51.4Volts
Memory Voltage2.20002.2000Volts
nForce SPP1.5001.500Volts
nForce MCP1.60001.5250Volts
Hypertransport Voltage1.3001.350Volts for the bus

Memory Timings

Swipe to scroll horizontally
Header Cell - Column 0 Memory TimingFalcon-NWBiohazardExplanation of the Timing
tCLCAS Latency45Delay between the CAS signal and the availability of valid data on the data pins (DQ)
tRCDRAS to CAS Delay44Delay before a read/write command after bank activation. The cells need to be stabilized by sense amplifiers for proper operation.
tRPRAS Precharge (Row to Row)44Time delay needed to close one row access and open a new one
tRASRAS Active to Precharge Delay1514Minimum RAS activation time delay or the time from the bank activate command until the precharge command an be executed.
CMDChip Select Issue Delay (Command Rate)22Time needed between the chip select signal and when commands can be issued to the RAM module IC.
tRRDRAS to RAS Delay (Between Banks)45Row to Row delay from one bank to one on another active bank
tRCRAS to RAS Delay - Bank Cycle Time (Same Bank)1334Row to Row delay on the same bank. One row discharges and another is activated. (Minimum time of tRAS = tRP)
tWRWrite Recovery Time46Delay between writes to ensure a proper writing to the cells. Ideally tRAS minus tRCD to ensure a premature RAS precharge does not wipe out the data.
tWTRWrite to Read Delay911The delay to prep the bus for read after a write. (Turn on or off the appropriate I/O buffers, clear existing data, etc.)
tREFDRAM Auto-Refresh Rate7.87.8Rate at with the DRAM's charge is refreshed in micro seconds. Prevents corruption by sending data to sense amplifiers and back to the refreshed cell.