Samsung Foundry is about to land an order from AMD to make the latter's processors using 3nm-class process technology with gate-all-around field effect transistors (GAAFETs), reports Korea Economic Daily. The information is strictly unofficial and should be taken with a grain of salt. Yet, if the report is accurate, this will mark the first time in recent years that AMD will dual-source its products.
AMD's chief executive, Lisa Su, reportedly said at ITF World 2024 that the company will mass-produce chips on a 3-nm-class GAA process, and the only company to offer such a production technology is Samsung Foundry. Unfortunately, it is unclear which products — CPUs (CCDs and/or IODs), GPUs, DPUs, chipsets, or maybe adaptive SoCs — AMD aims to produce at Samsung Foundry, though we would bet on some small chips initially to maximize yields.
"Lisa Su's comments are viewed as effectively formalizing AMD's 3nm foundry collaboration with Samsung," an industry source told Korea Economic Daily.
The move to use Samsung Foundry in addition to TSMC can be considered a strategic move for AMD as the company will expand its manufacturing capacity, sell more products, establish an important relationship, and gain leverage for price negotiations with TSMC.
For Samsung, securing AMD as a client is critical in closing the market share gap with TSMC. However, Samsung is so significantly behind the world's No. 1 contract maker of chips that it would take years to challenge the Taiwanese foundry. Nonetheless, this partnership could significantly boost Samsung's foundry business and enhance its competitive position in the semiconductor market.
GAAFETs offer several benefits over the currently used FinFETs. GAA transistors feature horizontal channels completely surrounded by gates. These channels are created through epitaxy and selective material removal, allowing designers to fine-tune them by adjusting the channel width: wider channels enhance performance, while narrower channels reduce power consumption. The architecture of GAAFETs can significantly decrease transistor leakage current (lowering power usage) and reduce variability in transistor performance, which is good for mobile processors and datacenter-grade products.
