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Alder Lake Chipsets Will Not Support PCIe Gen 5.0

Future CPU stock image Alder Lake-S
(Image credit: Photoshop)

It appears that Intel's 600 series chipset — built for Alder Lake — will not support the Gen 5.0 standard, per a report from HardwareTimes. According to a PCI-SIG certification, Intel's future Alder Lake-supported chipsets will max out at Gen 4.0 speeds running in an x4 configuration, meaning the only Gen 5.0 support Alder Lake will see is through the CPU lanes alone.

We don't know why Intel cut Gen 5.0 support from the 600 series chipsets, whether the it's cost issues or capability issues. Either way, this could be a positive strategy for Intel to keep Alder Lake motherboard prices at a minimum.

When Gen 4.0 first came out, we saw a large jump in motherboard prices due to the motherboards requiring much higher quality materials and far more PCB layers. These are both required to ensure Gen 4.0 speeds are stable. This is especially true of AMD's X570 platform which has full Gen 4.0 support on both the CPU lanes and chipset lanes. We can only imagine the same thing will happen with Gen 5.0, and probably be worse, since Gen 5.0 is significantly faster than Gen 4.0.

But with Intel supporting Gen 5.0 only on the CPU, motherboard prices may not be as expensive as they could be. It's much easier for motherboard manufacturers to build boards around one or two Gen 5.0 PCIe slots than to build the entire board to support Gen 5.0.

Plus, most consumers and prosumers are rarely saturating Gen 4.0 speeds right now, even on Gen 4.0 NVMe SSDs, and we don't expect this to change over the next few years. So this Gen 5.0 issue shouldn't be a problem for most buying into the Alder Lake platform next year.

  • hotaru.hino
    And really, is there any reason to have PCIe 5.0 soon (at least in the consumer space) when PCIe 4.0 capable systems haven't even surpassed PCIe 3.0 ones yet?
    Reply
  • ThatMouse
    The only thing PCIe 5.0 will be good for is GTA 6 load screens.
    Reply
  • kal326
    Not really surprising considering the 500 series chipsets didn’t have native 4.0 lanes either. So a 600 series doing the same with the chipset lanes prior gen only seems a solid rumor.
    Reply
  • InvalidError
    kal326 said:
    Not really surprising considering the 500 series chipsets didn’t have native 4.0 lanes either. So a 600 series doing the same with the chipset lanes prior gen only seems a solid rumor.
    It wouldn't make sense for the chipset to support a bunch of 5.0 connectivity when the chipset only has a 4.0x4 or 4.0x8 link to the CPU either. First-gen 5.0 PHYs will likely be power hogs too and we've all seen how happy people were with little chipset fans on X570 boards.
    Reply
  • kal326
    InvalidError said:
    It wouldn't make sense for the chipset to support a bunch of 5.0 connectivity when the chipset only has a 4.0x4 or 4.0x8 link to the CPU either. First-gen 5.0 PHYs will likely be power hogs too and we've all seen how happy people were with little chipset fans on X570 boards.
    I agree that 5.0 in the chipset doesn’t make sense any time soon. Outside tons of nvme, 4.0 doesn’t have a lot of usage now. Add into that graphics cards aren’t even hindered by 4.0 either.
    I wouldn’t be surprised if AMD stuck with 4.0 boards with Ryzen 4 as well. As for my X570, the fan doesn’t really bother me. It seems to only come on for a moment at cold boot.
    Reply
  • Makaveli
    Makes sense why Zen 4 is staying Pcie 4.0 + DDR5 in its first version.

    Most consumers won't see a benefit from 5.0 at the start. Servers and high end workstations are a different story.

    And this is a good reason for me to skip the first gen Zen 4 and wait for a refresh of that.
    Reply
  • vern72
    hotaru.hino said:
    And really, is there any reason to have PCIe 5.0 soon (at least in the consumer space) when PCIe 4.0 capable systems haven't even surpassed PCIe 3.0 ones yet?

    I'm surprised that PCIe 5.0 came out so soon after 4.0. I thought manufacturers would jump straight to 5.0 but I've heard it's significantly more expensive to manufacture 5.0 boards.
    Reply
  • InvalidError
    vern72 said:
    I'm surprised that PCIe 5.0 came out so soon after 4.0. I thought manufacturers would jump straight to 5.0 but I've heard it's significantly more expensive to manufacture 5.0 boards.
    I'm not surprised that 5.0 came out so soon, the need for something faster than 4.0 became imminent in the server space the instant NVMe SSDs became a thing. As for the expense of 5.0, every time you double the speed, you cut your combined timing, noise and other margins in half, which make specs that much more difficult to meet. What does surprise me is that the PCI-SIG has managed to increase bandwidth by 14X without changing the connectors.
    Reply
  • watzupken
    InvalidError said:
    I'm not surprised that 5.0 came out so soon, the need for something faster than 4.0 became imminent in the server space the instant NVMe SSDs became a thing. As for the expense of 5.0, every time you double the speed, you cut your combined timing, noise and other margins in half, which make specs that much more difficult to meet. What does surprise me is that the PCI-SIG has managed to increase bandwidth by 14X without changing the connectors.
    Server space, I agree. But Alder Lake is meant for consumers isn't it? May be Sapphire Rapids may arrive with PCI-E 5.0? On the consumer space, there are not that many users that can fully utilizing the PCI-E 4.0 bandwidth.
    Reply
  • JayNor
    Tom Lantzsch mentioned high end desktop chips a few times in his interview this week. The edge is becoming a first stage for processing camera streams and ai inference.

    Sapphire Rapids reportedly has 80 lanes of pcie5 and Alder Lake reportedly has 16 lanes of pcie5. We haven't seen if Alder Lake has enough logic to be a cxl slave. That would be interesting.

    Anyway ... the 16 lanes of pcie5 on Alder Lake-S are double the data rate of pcie4, and the 8 Gracemont cores have special instructions to support io. They are also being used in the Grand Ridge chips.
    Reply