Western Digital's BiCS5 112-Layer Tech Comes to TLC, QLC SSDs

Western Digital (WD) announced Thursday that it has finished the development of its fifth-generation 3D NAND technology, BiCS5, which is based on triple- and quad-level-cell (TLC and QLC) to deliver increased storage capacities at lower price points. 

WD expects some of its potential customers for these high-density SSDs will be companies storing connected car data, mobile device makers and AI companies.

"As we move into the next decade, a new approach to 3D NAND scaling is critical to continuing to meet the demands of the rising volume and velocity of data," Dr. Steve Paak, WD's SVP of memory technology and manufacturing, said in a statement accompanying the announcement. 

Paak added that by advancing WD's multi-tier memory hole technology for an increase in "density laterally, as well as adding more storage layers," the vendor has dramatically "scaled the capacity and performance of our 3D NAND technology, while continuing to deliver the reliability and cost which our customers expect."

WD has already started shipping TLC-based products using BiCS 512-bit technology but expects to ship much more significant volumes in the second half of 2020. It will make available a range of capacities for its TLC- and QLC-based NAND flash chips, including 1.33 terabit.

According to WD, the “lateral scaling” improvements to the BiCS5 technology combined with 112 layers of vertical memory offers multiple advantages over the company’s previous 96-layer BiCS4 technology. This includes a 40% increase in density (more bits per wafer), an optimized cost of production, as well as 50% higher I/O performance than the older technology.

WD partnered with Kioxia (formerly Toshiba Memory), to develop BiCS5. The companies will co-manufacture BiCS5 products at two joint-venture factories in Japan.