AMD released two Phenom models to the market on November 17: the Phenom 9500 and 9600, at 2.2 and 2.3 GHz respectively. These are both rated at a TDP of 95 W, which is close to the 105 W that Intel specifies for the Core 2 Quad Q6600 (2.4 GHz) and Q6700 (2.66 GHz). All faster models, which are scheduled for release in the first quarter of 2008, will be rated at 125 W. An overclocking-friendly Black Edition will be added near the end of this year, but it doesn't exceed the top speed of 2.3 GHz. However, AMD told us that it will be multiplier unlocked to provide ideal overclocking conditions, and that it won't be more expensive than the regular edition.

You can operate a Phenom processor in almost every Socket AM2 motherboard on the market. Even low-cost motherboards will support the standard thermal envelope of 95 W; you'll have to use an enthusiast platform for the 125 W versions, or if you intend to overclock your Phenom by a substantial amount. We're currently looking at the BIOS update situation, to check if it's actually as easy to deploy a Phenom into an existing Athlon system as AMD promises. Technically, it is still the same socket based on a 1,000 MHz HyperTransport interface; we'll see how this works soon in another article.

The microarchitecture behind Phenom has been known until now as K10, but is currently referred to as the Stars core. The most significant difference, as it highly influences the transistor count, certainly is the L3 cache, which is an extension to the twin-staged AMD64 cache design. While each processing core has its dedicated L1 data and instruction cache (64 kB each) as well as a 512 kB second-level cache, the L3 offers an additional 2 MB of super fast storage for all Phenom cores.

This isn't the first desktop processor to come with a third cache level: Intel's 3.2, 3.4 and 3.46 GHz Pentium 4 Extreme Editions, all of which were based on the 130 nm Gallatin core, also included a 2 MB L3 cache (along with a 512 kB L2 cache). Unlike from the Pentium 4 EE's L3 cache, though, the Phenom's third level cache works as a write buffer for the main memory.

AMD also introduced improvements in the cores' branch prediction units, a so-called sideband stack optimizer to update the ESP (enhanced stack pointer) without requiring processor time, a memory prefetcher that is capable of loading data exclusively into the L1 cache bypassing the L2 cache (hence not flushing content), 128-bit SSE, and a 32-byte instruction fetch buffer. Virtualization technology has been around for months now, and is also part of every Phenom.

Support for 1.8 GHz HyperTransport 3.0 is the last performance feature that was added with Phenom. While HT 2.0 at 1.0 GHz upstream and downstream supports a 8.0 GB/s bandwidth, HT 3.0 enables up to 20.8 GB/s throughput. This will be important in the future if four or more cores access other core items such as the memory or a PCI Express device, such as a graphics card.