According to a new, but unverified leak, Intel may be bringing its hybrid architecture from Lakefield to the desktop with Alder Lake-S on 10nm. In an implementation scheme that's known in the smartphone world known as big.Little, it would have eight big and eight small cores.
The leak comes via Twitter user @momomo_us via Sharkbay, who has often published about unreleased products, but should be treated with caution. Nonetheless, it provides an interesting possibility that big.Little could come to the desktop.
According to the information, Alder Lake-S will land on a new LGA1700 socket and the highest-end, big.Little configuration will become available with an 80W or 125W TDP. According to the notes, Intel is also “investigating performance scaling up to 150W.” The chip purportedly consists of eight small cores and eight big cores.
Since this year’s 10nm+ Tiger Lake will receive the Willow Cove cores, it is likely that Alder Lake will be equipped with the next-generation Golden Cove cores. Golden Cove will have increased IPC, AI and network performance and security features, according to Intel. For the small cores, Intel might integrate next-generation Gracemont cores, which will features increased IPC, frequency and vector performance.
There would also be a six-core version without the small cores. Also according to the leak, all configurations will receive GT1 integrated graphics. It is further assumed that Alder Lake will be manufactured on Intel’s improved 10nm++ process.
Alder Lake-S would succeed Rocket Lake-S, which will succeed the upcoming Comet Lake-S processors with up to 10 cores. Rocket Lake-S is rumored to introduce AVX-512 and PCIe 4.0.
Hybrid architecture on the desktop
It has long been a question if Intel would release 10nm products for the desktop, as Ice Lake and Tiger Lake are both focused on mobile. Bits and pieces of hints about Alder Lake-S have since trickled out. The latest leak about Alder Lake-S being released in a big.Little configuration provides a new perspective on Intel’s possible plans.
Intel first started talking about big.Little in late 2018 when it unveiled Lakefield for ultra-low power designs, but Intel calls it a hybrid architecture. In Lakefield, four Atom Tremont cores are combined with one high-performance Sunny Cove cores. Naturally the question arises why Intel would bring this to its highest-performance desktop SKU.
One possibility could be that this is more of a temporary stopgap until 7nm. Intel has found itself in a core count war with AMD, who has released 16 cores on its mainstream platform, and up to 64 cores on its high-end desktop (HEDT) platform.
Intel might have planned to include only eight cores in Alder Lake-S initially, but perhaps decided to also include eight smaller cores as a compromise: this would provide additional multi-threaded performance, but by using smaller Atom cores, it would not burden the 10nm process as much as 16 big cores, since Intel’s 10nm process is not expected to yield as high as 22nm and 14nm.
Intel provided some details about its implementation at HotChips last year when it discussed Lakefield.
In Intel’s implementation, the performance-critical threads are scheduled on the Sunny Cove core, while the background threads go to the Tremont cores. When multi-threaded applications are executed, all cores are involved. Intel provided an example of web browsing.
There is also a software and OS component, as dynamic feedback is provided to the software on the power and performance capabilities, but the slide is not clear if applications would have to be explicitly programmed to take advantage of the big and small cores simultaneously. It is also not known yet to what extent they would have the same instruction set, as Atom currently lacks AVX SIMD vector instructions, although this could change with Gracemont.
This makes it is difficult to tell how much additional performance this implementation would provide for the desktop and how useful it would be. While Atom cores are typically relegated to Intel’s cheapest processors, Intel has increased its investments in Atom, though. Tremont on average increased IPC by 30% compared to Goldmont Plus.
If Intel was unwilling to commit to 16 big cores on its 10nm process, then it might have deemed adding eight Atom cores a compromise. Reviews would have to evaluate this. The first hybrid architecture Lakefield designs will come to market later this year, likely around Computex.
Does any version of Windows handle big.LITTLE at all or well? Microsoft seems to be having problems with the Windows Scheduler. NUMA, lots of cores, ... now, possibly, heterogeneous cores? Intel can spend more on software developer support than AMD, but would they have it working well while Alder Lake is relevant?
If the small cores also had support for SIMD stuff to supplement the big cores in MT tasks this might be competitive with 12 core AMD stuff in MT and have an advantage in less well threaded stuff assuming the clocks are decent and there's like a 30% IPC increase over Sky Lake.
I presume this would also get rid of the mitigations for side channel attacks associated with hyperthreading.
Lakefield design looks pretty well !!