First spotted by the folks over at CPU World, the document provides detailed information about the 32 nm, 3.1 billion transistor CPUs.
Among the new features of the processor is Intel's Instruction Replay Technology, which allows the CPU to recover from pipeline errors much faster as the execution does not rely on an entire pipeline flush, but simply restarts at the last known correct position.
The document also provides information about dual domain (front-end/back-end) hyper-threading, which makes its debut with Poulson. According to the manufacturer, the expanded hyper-threading approach, which will still allow two threads per physical processor, and the decoupled pipeline enable instruction fetch and instruction execution to operate independently and run much more efficiently: For example, the front-end can perform instruction fetch for either thread regardless of which thread the back-end is executing.
Intel was originally expected to launch Poulson sometime in Q2 of 2012.
