Intel Lunar Lake Core Types Seemingly Confirmed by PerfMon
First details about Intel's Lunar Lake revealed
While Intel has revealed that its codenamed Lunar Lake processor due in 2024 will be based on a brand-new microarchitecture that will deliver unprecedented performance-per-watt efficiency, it never disclosed anything else about the CPU. Yet, the latest update of Intel's PerfMon software (discovered by @InstLatX64) fills some gaps.
As it turns out, Intel's Lunar Lake will pack Lion Cove high-performance cores as well as Skymont energy-efficient cores. The software does not disclose core count or peculiarities of the Lion Cove and the Skymont microarchitectures, but it clearly reveals that the upcoming Lunar Lake processor will indeed use all-new microarchitectures and, at least based on Intel's claims, will deliver unprecedented performance efficiency.
Row 0 - Cell 0 | P-Core | E-Core |
Alder Lake | Golden Cove | Gracemont |
Raptor Lake | Raptor Cove | Gracemont |
Meteor Lake | Redwood Cove | Crestmont |
Arrow Lake | ? | Crestmont |
Lunar Lake | Lion Cove | Skymont |
Intel's Lunar Lake will inherit disaggregated multi-chiplet design from Meteor Lake and Arrow Lake client CPUs, but it is expected (based on the schematic images that Intel is publishing) bring it to a new level and split the things up a bit further. Also, Intel's Lunar Lake will use the company's 18A (1.8nm-class) fabrication process for its compute tile, which will enable Intel pack in more RibbonFET transistors and improve performance thanks to backside power delivery.
For now, it is hard to estimate performance advantages enabled by the new Lion Cove and Skymont microarchitectures as well as Intel 18A process technology over Arrow Lake CPU, but Intel itself sets pretty high expectations for its 2024 CPU part.
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Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.