Intel released a new development guide for game developers to optimize PC games for Alder Lake's new hybrid core architecture featuring performance and efficiency cores. The guide is very in-depth, as it discloses a multitude of ways that you can push workloads to specific core clusters.
The goal of optimizing code for Alder Lake's hybrid layout is to ensure the performance cores are doing all the heavy lifting while the efficiency cores handle all the light workloads and background tasks.
To simplify the programming model for developers, all performance cores and efficiency cores have the same instruction set, meaning both clusters of cores can handle the same workloads. The exception to this is AVX-512, which is only supported on the performance cores. To enable AVX-512 support, you will need to disable the efficiency cores within the BIOS.
There will also be several core configurations developers should be aware of when optimizing for Alder Lake. Intel details two configurations for desktop chips: 6C + 0A (no efficiency cores), and 8C + 8A. Laptop chips meanwhile will feature different configurations including: 2C + 8A and 6C + 8A.
Intel's Alder Lake CPUs will be running on a new scheduler, called the Intel Thread Director (ITD). Its job is to provide Instruction Set Architecture (ISA) awareness to the operating system, which allows the ITD to pair tasks with the proper cores.
ISA is a feature that allows Windows to see the performance characteristics of each core cluster. If ISA did not exist, Windows would believe all cores on Alder Lake perform the same and assign workloads to the wrong set of cores.
Developers will have the option to heavily utilize the ITD to do the work for them. Alternatively, they can use several Intel-created tools to manually set CPU affinity, prioritization, and scheduling for the game they are creating. This could be beneficial for further optimizing a game if Alder Lake's ITD isn't doing the job.
Things can get complicated for game developers when choosing which game tasks are assigned to specific cores. Things like render tasks should go to performance cores to get the job done quickly, and background processes can be completed on the efficiency cores. Some scenarios also benefit from disabling the efficiency cores entirely to give as much power as possible to the performance cores.
There's also the challenge of making sure the performance cores are not entirely maxed out. Intel specifies that tapping into the efficiency cores when the performance cores are overloaded is optimal to ensure that the entire CPU is utilized.
Overall, the amount of optimizing developers can perform with Alder Lake is nearly endless. This could impact launch day performance results due to bad optimizations at the start. But as time goes on, we should see developers getting the hang of intel's new hybrid architecture and see a general performance increase.
Or is this some intel serial code.
Intel can't name stuff w/o gibberish in it anymore.
Most of the work will be done at the engine level and a lot of it can be automated. While running uncomplicated code that doesn't branch all over the place, the Gracemont cores can probably perform nearly as well as the Golden Cove cores. When you notice that the small cores are suffering many pipeline stalls on a given thread, you promote it to the big cores.
It should be pretty trivial to move this same concept over to alder.
If this would be AMD you would have to wait optimizations many years, if ever. Just look the win11 situation... that is luckily getting better... soonish...
Devs only optimize for systems that would otherwise be unable to properly run the software, in other words consoles, and now with consoles becoming strong enough maybe they will stop optimizing all together other then for PR reasons on special occasions. This has ben the case for applications as well for years, there are extremely few that are optimized in any way beyond what the compilers do on their own.