JEDEC has published a new revision of the LPDDR5 standard (JESD209-5B) that covers some performance and power improvements to the original specification as well as LPDDR5X, an extension to LPDDR5 that increases a maximum data transfer rate to 8533 MT/s. LPDDR5 and LPDDR5X will co-exist and complement each other on the market.
LPDDR5 and LPDDR5X are pin-to-pin compatible, greatly simplifying development of system-on-chips (SoCs) and platforms supporting the new type of memory. To enable higher data transfer rates and increase reliability of the upcoming low-power memory subsystems, LPDDR5X introduces pre-emphasis function to improve the signal-to-noise ratio (to enable higher clocks and performance improvements) and reduce the bit error rate as well as adaptive refresh management, and per-pin decision feedback equalizer (DFE) to enhance robustness of the memory channel (a page taken from the DDR5 standard).
LPDDR5 features data rates of up to 6400 MT/s, so LPDDR5X provides a robust 33% performance improvement with its 8533 MT/s data date. The performance enhancement will be welcome by bandwidth-hungry applications, such as AI/ML and graphics processing. Also, if LPDDR5X gains support for PCs SoCs, these computers may get memory bandwidth not accessible even by machines using DDR5 memory, which will be a huge benefit, particularly for integrated graphics.
So far, LPDDR5X has been endorsed by Micron and Samsung, so expect these companies to offer appropriate chips when there is demand. Meanwhile, Synopsys will offer IP (memory controller, PHY) to enable developers of SoCs to add support of LPDDR5X to their designs.
"In lockstep with JEDEC's LPDDR5/5X standardization process, Samsung also has been working closely with leading manufacturers to pave the road for the next generation of smartphones, laptops and other mobile computing devices," said Doohee Hwang, principal engineer for mobile DRAM product planning, Samsung Electronics.
Since the LPDDR5X proposal has been around for some time, it is reasonable to expect that the new memory standard will be adopted by SoC designers and makers of actual hardware sooner rather than later, especially considering how bandwidth hungry modern SoCs are for high-performance applications. Still, it is hard to tell when we are going to see the first LPDDR5X-enabled devices on the market.
"As a leader in low-power memory, Micron collaborated closely with other JEDEC members to define LPDDR5X, providing the mobile ecosystem a critical advancement in higher bandwidth," said Osamu Nagashima, Micron senior manager of mobile systems architecture and vice chair of the JEDEC low power memories subcommittee. "LPDDR5X's higher speed interface will open doors to new 5G and AI use cases, delivering better user experiences across memory-intensive applications such as gaming, photography and streaming media."
