Kioxia Demos HLC 3D NAND and Talks About OLC NAND

(Image credit: Kioxia)

The best SSDs currently use TLC or maybe QLC memory. Kioxia (formerly Toshiba Memory) was the first 3D NAND maker to start talking about 5-bits-per-cell (5 bpc) PLC (penta level cell) 3D NAND memory back in 2019. Kioxia's scientists and engineers certainly don't want to rest on their laurels, and this year they demonstrated operation of 6 bpc — hexa level cell, or HLC — 3D NAND memory and believe that even 8 bpc — octa level cell, or OLD — 3D NAND is possible. But there are some important nuances. 

To store more than one bit per cell, NAND memory has to hold multiple distinct voltage levels in that cell. For example, MLC has four states per cell, TLC uses eight voltage levels, QLC has 16 voltage levels, and PLC has 32 voltage states. In other words, two taken to the power of whatever cell level you're talking about. To store six bits per cell (HLC), that cell has to hold 2^6, or 64 voltage levels.

To build 3D NAND with such cells, manufacturers have to overcome multiple challenges. They have to find the right materials that can handle storing 64 different voltage states, while also being able to differentiate between those states. That's means the voltage states can't interfere with each other. Keeping temperatures in check is also important and becomes increasingly difficult at higher bits per cell.

To demonstrate the possibility of HLC memory, Kioxia's scientists took one of the company's existing 3D NAND memory chips and immersed it in liquid nitrogen (77K, -196°C) to eliminate deterioration of the cells caused by rewrite cycles. The extremely low temperatures also help to reduce the need for tunnel insulating films, lower the voltage requirements, and stabilize the materials. All together, this improves the physical properties and processes that take place in the IC.

Kioxia's scientists said that they not only managed to write and read six bits of data from one cell and reliably hold it for 100 minutes, but they also were able to achieve a 1,000 program/erase (P/E) cycles endurance. Of course, that's largely thanks to the -196C temperatures. In normal conditions, endurance of 3D HLC NAND memory would be around 100 P/E cycles, according to its estimates. Kioxia presented results of the experiment at the 5th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2021) in April 2021 (presentation number: WE2P4-5), reports PC Watch

3D PLC NAND has not been commercialized yet, and Western Digital (Kioxia's manufacturing partner) believes it will only make sense for some SSDs after 2025. Western Digital further claims that 3D PLC brings too many issues for a mere 25% density increase.

In contrast, 3D HLC NAND increases flash memory density by 50% compared to 3D QLC NAND, so it's more likely to be commercially feasible. Furthermore, scientists from Kioxia believe that even eight bits per cell OLC 3D NAND with 256 voltage levels is technologically possible. The task for scientists and developers now is to find the right materials, design, and controllers to make 3D HLC and 3D OLC NAND operational and commercially feasible at room temperatures. 

If they fail, development of multi-level cell 3D NAND will stop at PLC and makers of flash will have to focus on increasing the number of layers in 3D NAND flash to increase memory density. Granted, Samsung and SK Hynix believe that 600 to 1,000 layers are feasible, which already opens the doors to very high capacity SSDs.

Even if Kioxia's scientists succeed in making HLC and OLC NAND work at room temperatures, they will also have to develop appropriate controllers that will be able to reliably read and write data from such flash memory. Such controllers will have to support extremely complex ECC algorithms that will require significant compute horsepower. Will such controllers be too expensive and offset the capacity advantages of 3D HLC and 3D OLC NAND? And what sort of performance could future HLC drives even offer? We already know that even QLC drives tend to perform rather poorly in heavier use cases. Only time will tell, but we don't expect TLC to fade away any time soon.

Anton Shilov
Contributing Writer

Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.

  • 2Be_or_Not2Be
    I like the research - testing the limits of what might be possible. But I'd much rather research go into technology that is an upgrade performance-wise, than yet another downgrade in both performance & durability.
  • 1_rick
    " To store six bits per cell (HLC), that cell has to hold 2^6, or 64 voltage levels. "

    Well, not quite. I get what you're saying, but it's poorly written. It's more accurate to say "to be able to store n bits per cell, the cell has to be able to reliably store and distinguish between 2^n different voltage levels, any one of which the cell will maintain at any given time." If it can't maintain the voltage within whatever precision it requires, or it can't properly read the voltage, it will lose data. Hexabit cells would have 64 different potential voltages, with a difference of 0.078 volts between any two adjacent values. So storing a 7 (000111) is a voltage of 0.546875, and an 8 (001000) is .0625v. If the cell degrades so that it can't maintain the voltage with the required precision (e.g., it's storing 0.6v--or it's storing 0.62v, but the reading circuit thinks it's got an 0.6v) then it can't accurately remember whether it's got a 7, an 8, or something else.)

    Edit: admittedly, subsequent paragraphs do a better job of explaining it. To give a more specific example, it's common that 5v logic chips (like 7400-series TTL) might specify that a voltage under 0.8v is a logic 0 and anything over 2v is a logic 1 (I got those values from the datasheet for a 74193). A voltage of 1.5 is out of spec and indeterminate--if you feed that into it, you can't predict what will come out.)
  • ravewulf
    I'd rather focus on the durability aspect and scale up in terms of layers or additional PCB space for chips than increasing how many bits per cell. Either that or change to different materials/technology that can store multiple values without the significant drop in durability we're currently seeing.