Manufacturers of NAND flash memory have always tried to increase the storage density of their memory devices by increasing the number of bits stored per cell. While fundamentally, this is the most challenging way of increasing recording densities, it is also the most rewarding one from a cost standpoint. Companies like Kioxia are constantly experimenting with the number of bits they can store in one cell. This year the company said it had managed to store seven bits per cell (7 bpc), albeit in the lab and under low temperatures.
To store more than one bit, the NAND cell must hold multiple distinct voltage levels, which is challenging as NAND makers have to find the suitable materials for these cells and then record and read them without errors. Moreover, the number of voltage states increases exponentially with the number of bits. For example, to store four bits, the cell has to hold 16 voltage levels (2^4), but with six bits, that number grows to 64 (2^6). Kioxia's achievement of storing seven bits per cell requires holding 128 voltage states (2^7). Kioxia presented the paper describing its achievement at the International Memory Workshop 2022 (IMW 2022).
Kioxia had to use a single-crystal silicon channel built using epitaxial growth to store seven bits per cell. Single-crystal silicon has lower electrical resistance than polycrystalline silicon, making it easier to record such cells. Furthermore, the subthreshold slope of cell transistors featuring single-crystal silicon is steeper (compared to conventional transistors), whereas leakage current and read noise are lower, reports PC Watch.
Such NAND flash cells are not available commercially nowadays, so scientists from Kioxia had to make them in the lab. Furthermore, to record and read them, they submerged the chips in liquid nitrogen (it in liquid nitrogen (77°K, -196°C) to stabilize the materials, lower the voltage requirements, reduce the need for tunnel insulating films, and avoid depreciation of the cells caused by rewrite cycles.
Building custom transistors in the lab is only half of the challenge with ultra-dense NAND flash memory. First, researchers had to develop and use a custom controller with a custom encoding scheme suitable for handling 128 voltage states.
NAND flash controllers have become increasingly complex since multi-level cell (MLC, 2 bpc) NAND debuted in the early 2000s. Hence, controller complexity is something that both NAND producers and controller developers are familiar with. But controllers capable of processing 128 voltage levels accurately might be as complex as microprocessors and just as expensive. Hence, the main question is whether it makes sense to use a costly and sophisticated SSD controller to increase 3D NAND recording density by merely 40% (going from 5 bpc to 7 bpc). While the best SSDs tend to cost a lot, a too advanced controller could make ultra-high-capacity drivers prohibitively expensive and eliminate all of their advantages.
Western Digital believes that even PLC 3D NAND (5 bpc) will barely make sense even after 2025. But Kioxia now demonstrates the physical possibility of storing seven bits per cell and even talks about keeping eight bits per cell eventually.
