Igor's Lab has some new information on AMD's forthcoming EPYC (codename Milan) processors. The site claims that fresh server chips are slated to replace the EPYC 7002-series (codename Rome) later this year.
We already know from AMD's official disclosures that Milan, which probably adopts the EPYC 7003-series moniker, will undoubtedly debut with AMD's next-generation Zen 3 microarchitecture. Predictably, AMD will continue to tap TSMC's manufacturing abilities for Milan. Word around town is that the third-generation EPYC processors would benefit from the foundry's improved 7nm+ process node, but both the foundry and AMD have changed the name of the 7nm+ node on their respective roadmaps, so that remains up for debate.
According to the leak, despite being on a new microarchitecture, Milan will slot fine into the existing Socket SP3. However, Milan is the last wave of EPYC parts to grace the socket as its successor (codename Genoa) is expected to usher in the new Socket SP5. In regards to the primary leaked specifications, Milan shouldn't deviate much from Rome. The Zen 3 processors still max out at 64 cores, come with support for eight DDR4 memory channels, DDR4-3200 modules and high-speed PCIe 4.0 lanes.
The specifications from Igor's report are for the A0 stepping silicon, meaning these are early engineering samples. While we don't expect the core or thread count to differ, the clock speeds will likely improve with the final silicon. As with any leak, there's also the possibility the information is incorrect, but the details largely line up with our expectations for the EPYC Milan chips.
|Header Cell - Column 0||100-000000114-07||100-000000114-09||100-000000117-03|
|Design||8 x 1 x 8||8 x 1 x 8||4 x 1 x 8|
|Cores / Threads||64 / 128||64 / 128||32 / 64|
|Boost Clock (GHz)||2.2||3.0||3.0|
|L1 Cache (MB)||2||2||1|
|L2 Cache (MB)||32||32||16|
|L3 Cache (MB)||256||256||128|
|TDP / Max TDP (W)||225 / 240||225 / 240||180 / 200|
*Specifications are unconfirmed.
The 64-core models (100-000000114-07 and 100-000000114-09) reportedly use a 8+1 design, meaning eight Zen 3 Core Complex Dies (CCDs) and one I/O die. The 32-core model's composition, on the other hand, comprises of four Zen 3 CCDs and one I/O die.
The 64-core SKUs apparently have 2MB of L1 cache, 32MB of L2 cache and 256MB of L3 cache. The 32-core part has halved of the 64-core's cache. At first glance, Milan has the same amount of cache as Rome. However, we already know from an official AMD presentation that the compnay has made significant improvements to the cache design on Zen 3 behind closed doors.
On Zen 2, each CCD consists of two Core Complexes (CCXs), and each CCX has four cores equipped with 16MB of L3 cache. For Zen 3, AMD revamped the CCX to eight cores that are linked to 32MB of L3 cache. The new design aims to help eradicate latency and improve overall instruction per cycle (IPC).
The 64-core and 32-core Milan ES samples allegedly boost up to 3 GHz. The clock speed isn't far off from Rome's maximum boost clock for 64-core and 32-core SKUs, which is 3.4 GHz. The combination of AMD's Zen 3 microarchitecture and TSMC's matured 7nm manufacturing process should give us Milan chips with equal or superior boost clock speeds in comparison to Rome.
According to AMD's roadmap, Milan will come with a similar 120W to 225W package as Rome. At the current rumored clock speeds, Igor's sources claim that the 64-core and 32-core parts could have a 225W and 180W TDP (thermal design power), respectively.
Milan might just be a simple refresh until Genoa lands at some point in 2021, however, it's a refresh done right.
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Zhiye Liu is a Freelance News Writer at Tom’s Hardware US. Although he loves everything that’s hardware, he has a soft spot for CPUs, GPUs, and RAM.
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