Nvidia recently posted a series of job listings for people with experience working with the open-source RISC-V (short for Reduced Instruction Set Computer - 5) instruction set architecture (ISA).
Nvidia made it public in 2016 that it was creating its own RISC-V microcontroller for its GPUs, but these new job openings allude to Nvidia possibly planning something bigger with the RISC-V ISA.
Synced Review, a Chinese media entity that covers news in the machine learning field, was the first to notice report on the job offerings. It said Nvidia posted listings for these jobs in its Shanghai headquarters: Senior CPU Architecture Engineer (RISC-V / Security); Senior Video Codec Architecture Engineer; Senior Video Codec IC Design Engineer; Senior CPU Design Engineer (RISC-V / Security); Senior IC Verification Engineer (Image Processing ISP) and Senior IC Verification Engineer (Video Codec).
According to Synced, Nvidia’s job posting for Senior CPU Architecture Engineer said: “Applicants should have in-depth understanding of the application scenarios of different subsystems in Nvidia GPUs and define the architecture for Nvidia RISC-V processor.”
In another job posting on LinkedIn, Nvidia stipulated that the RISC-V processors need to be integrated with the Tegra System-on-Chip (SoC) and Nvidia GPUs.
Nvidia is also looking for Senior CPU Design Engineer candidates who can “participate in the design and implementation of Nvidia's next-generation RISC-V CPU for security.”
The latter feature may be something that Nvidia wants specifically for its automotive-focused chips, but it may also be something Nvidia plans to use across a range of products.
Nvidia recently presented a scalable multi-chip module (MCM) inference research chip that uses an open source RISC-V Rocket control processor. The chip configures communication between the Processing Elements (PEs) of the MCM and global buffers via software-managed registers.
Nvidia’s new vacancies may indicate that the company is interested in building something more ambitious than a microcontroller for its GPUs or inference chips. It’s possible it's working on a RISC-V replacement of its Arm-based Denver core (currently used in Tegra/Xavier SoCs), but we may not know for a few years.
