
The 7nm process is reaching its peak. Nvidia's rumored to start placing orders at TSMC and Samsung for releasing its next-generation 'Ampere' graphics cards mid-2020. Meanwhile, we already know that TSMC is investing heavily in 5nm fabrication, with Apple purportedly having reserved two-thirds of TSMC's 5nm capacity for the A14 SoC expected to power the iPhone 12.
Now, Samsung has succeeded in making the first strides towards the 3nm process, as reported by the Korean Maeil Economy this week. According to the report, Samsung's goal is to become the world's number one semiconductor manufacturer by 2030.
Samsung's work on the 3nm process is based on the Gate All Around (GAAFET) technology rather than FinFET. This supposedly reduces the total silicon size by 35% while using about 50% less power and allows for the same amount of power consumption and 33% performance increase over the 5nm FinFET process.
We first heard that Samsung was working on the 3nm GAAFET process a year ago, when it said that it targeted mass production in 2021. That was considered ambitious at the time, but if Samsung has already succeeded in producing its first 3nm prototypes, the vendor might be closer than expected.

The GAAFET design differs from the FinFET design in that it is built around having gates around four sides of the channel, which ensures reduced power leakage and thus improved control over the channel -- a fundamental step when shrinking the process node. This switch to a more efficient transistor design paired with the decreased node size is what enables the tremendous jump in performance per watt over a 5nm FinFET process.
Between then and now, what happened that allowed them to break that barrier?
The light was the main issue for getting to 7nm so they are using EUV. Well TSMC's first 7nm node is using quad patterning(think like using a stencil to spray paint letters but you have to apply 4 times) but it's not that great. There next node is using EUV which is what iPhone APU's are made with. They can use traditional FinFET designs and extreme ultraviolet light to get down to 5nm. After that they have to use this gate all around approach which involves all sorts of tech like nano wires. You can think of CPU designs going 3d so to speak to overcome these physical limitations. What this does is give a contact area that is larger than the smallest feature sizes so you don't run into physical limits.
The photo in the article should help visualize.
Eventually head-room may run out with existing materials (and assuming no cost-effective advancement with new materials), it may be possible to push frequency up by using more fault-tolerant and/or redundant designs. This is already the status-quo with ECC DRAM and cutting-edge quantum electronics, etc., so at least there is some precedent to guess all will be well down to 1-1.5nm. Below that, I don't think there is enough information currently available to speculate what is cost-effectively possible.
https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithography