Toshiba Unveils 48-Layer BiCS 3D NAND

Toshiba announced that it is shipping samples of its 48-layer three-dimensional BiCS (Bit Cost Scalable) stacked cell structure flash. In simpler terms, BiCS is Toshiba's own spin on 3D NAND. The new Toshiba flash comes in 128 Gbit (16 GB) die with 2-bits-per-cell, which is the same number of bits-per-cell compared to standard 2D planar MLC NAND. 

The move to 3D NAND structures is inevitable, as standard planar NAND (2D) is running against a developmental wall. As NAND lithography shrinks, the errors begin to multiply while endurance plummets. The only way out, for now, is up. Current 2D NAND spreads the cells out flat like a checkerboard, but 3D NAND stacks the cells vertically, much like rooms and floors in a hotel. This new vertical architecture solves many of the problems associated with increasing NAND density.

Toshiba's new BiCS NAND will increase endurance and performance while reducing power consumption. Several companies are bringing 3D NAND to market, and each has a unique design that will lower cost in the long term by packing more transistors into a smaller space, thus producing a cheaper product.

Toshiba, which actually invented NAND, collaborates with SanDisk to produce NAND products through the Flash Forward Ltd joint venture. The team has had BiCS in the pipeline for quite some time; development was originally announced back in June 2007. Toshiba has spent considerable time optimizing BiCS for mass production and has been vocal that it would not bring BiCS to market until it is cost-competitive with planar products (i.e. profitable).

Samsung was the first to market with its 3D V-NAND, and it's already shipping finished SSD products. Samsung has already progressed through two generations of V-NAND; the initial 24-layer design features 128 Gbit die, and the second-generation 32-layer design features 86 Gbit die. Many industry analysts have opined that Samsung is likely not pulling the best yields, or profit, from its current-gen V-NAND products, but that remains speculation.

Samsung goes it alone in the NAND world, but it is competing with another tag team with impressive clout. The Intel/Micron IMFT (Intel-Micron Flash Technologies) partnership is bringing its 3D NAND products to bear, and currently it has the density advantage. Details are scarce on the IMFT offering, but we do know that it features 32 layers and an impressive density of 256 Gbit (32 GB) for the MLC version. IMFT will also offer a 3D TLC part with an amazing die density of 384 Gbit (48 GB). Intel indicated at its Investor Meeting that shipments will begin in the second half of 2015.

SK Hynix is the wild card. The last known information had it developing a vertical floating-gate structure termed "DC-SF." This unique design will continue to utilize the floating gate, whereas others have moved on to charge trap. SK Hynix projects production in 2016.

There is no word on the BiCS lithography, and neither IMFT nor Samsung have released this information on their respective 3D NAND products, either. All 3D NAND products feature a relaxed lithography, some speculate Samsung V-NAND is 3x nm (30-39 nm), but as the products mature into successive generations the manufacturers will shrink lithography and stack the cells higher. Toshiba has the stacking lead with its 42-layer design, and we expect that a 3-bits-per-cell (TLC) BiCS announcement will come in the future.

Toshiba is readying Fab2 at Yokkaichi Operations in Mie prefecture, Japan for BiCS mass production. Clean rooms are being built in phases, and construction will be complete in the first half of 2016. Toshiba is starting sample shipments of the new product today.

This new wave of 3D NAND products will increase competition as the fabs ramp production, and we can expect a flurry of announcements and releases as the year wears on.

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Paul Alcorn
Managing Editor: News and Emerging Tech

Paul Alcorn is the Managing Editor: News and Emerging Tech for Tom's Hardware US. He also writes news and reviews on CPUs, storage, and enterprise hardware.