Panther Cove will reportedly arrive with big IPC improvements, support for Intel APX

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Panther Cove is one of the furthest out P-core CPU architectures being designed by Intel

Lunar Lake CPU
(Image credit: Intel)

It's not slated to arrive anytime soon, but a P-core architecture that Intel is working on will purportedly boast big IPC improvements, as well as support Intel's new APX instruction set. This information was discovered by INstLatX64 on X.

According to a user on the real world technologies forum, Panther Cove will represent a big architectural overhaul of Intel's P-core design, featuring "large IPC" improvements as well as support for Intel's APX and AVX10 standards. Panther Cove is one of the furthest out architectures Intel is purportedly working on, and is purportedly expected to arrive after Cougar Cove, which is itself slated to land after Lion Cove, a P-Core architecture powering Core Ultra 200 series Lunar Lake and Arrow Lake CPUs.

The forum user notes that Intel's development strategy with its P-core architectures harkens back to its "tick-tock" architectural development the company was known for during the 2010s where one major architectural change was succeeded by one minor architectural update before the cycle restarts for the next architecture design.

As a result, the forum user discloses that Cougar Cove will be an update "tock" of Lion Cove that we have right now with Lunar Lake and Arrow Lake. Panther Lake will be the next major "tick" in Intel's architectural cycle, which would explain the claims about big IPC improvements.

The most interesting tidbit about Panther Cove is the addition of Intel APX. APX stands for Intel Advanced Performance Extensions and serves as an extension of the entire x86 instruction set. According to Intel, APX adds more registers and various new features that improve general-purpose performance, without significantly increasing power consumption or silicon area.

Specifically, APX doubles the amount of general-purpose registers from 16 to 32, which allows the compiler to keep more values in registers. APX also adds new conditional forms of load, store, and compare/test instructions to help offset the performance issues of out-of-order CPUs, which take advantage of branch predictors. These conditional forms purportedly cut down on the number of branches that may incur misprediction penalties.

It is unknown what CPU architecture Panther Cove will reside in, but if Intel's timeline stays consistent, we could see Panther Cove in the Core Ultra 400 series.

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Aaron Klotz
Aaron Klotz
Contributing Writer

Aaron Klotz is a contributing writer for Tom’s Hardware, covering news related to computer hardware such as CPUs, and graphics cards.

42 Comments Comment from the forums
  • federal
    Intel returning to "tick tock" releases? They've kind of caught up to AMD and TSMC after a years long mad scramble (assuming 18a really has been proven at this point and is entering early production). Maybe this is a sign that they're feeling more confident and settling in for a more predictable and sustainable future. For their sake, I hope not too confident...
    Reply
  • usertests
    Maybe AMD should be the one charting the course of x86 with instruction set changes. I guess this is the benefit of having over 100k employees.
    Reply
  • ThomasKinsley
    It's not great that Intel is pinning all its hopes on 18A. I guess we'll see how that works out. On a side note, I always felt it was better to buy during Intel's "tick" cycle. The toks seemed like a wasted year to me.
    Reply
  • Mama Changa
    Cougar cove is the all new P core for Panther Lake, it is not a tweak of Lion cove. Panther cove would have to be for Nova Lake in late 2026, and then would be on 16A or 14A I presume, as Panther Lake is on 18A along wth Clear Water Forest.

    What would you prefer they pin their hopes on? 18A if successful is more advanced than anything TSMC has and will put Intel more than a generation ahead of AMD that only gets N3 on Zen 6 and N2 for Epyc maybe in late 2026 early 2027. AMD won't get n2 for desktop until Zen 7 at which point Intel will be on 14A.
    Reply
  • Thunder64
    Mama Changa said:
    Cougar cove is the all new P core for Panther Lake, it is not a tweak of Lion cove. Panther cove would have to be for Nova Lake in late 2026, and then would be on 16A or 14A I presume, as Panther Lake is on 18A along wth Clear Water Forest.

    What would you prefer they pin their hopes on? 18A if successful is more advanced than anything TSMC has and will put Intel more than a generation ahead of AMD that only gets N3 on Zen 6 and N2 for Epyc maybe in late 2026 early 2027. AMD won't get n2 for desktop until Zen 7 at which point Intel will be on 14A.

    Because Intel has executed so well with processes this past decade, including most recently canceling 20A and fabbing ARL at TSMC.

    I’ll believe it when I see it.
    Reply
  • Kondamin
    I doubt things will be going as smooth as they have for the next couple of years that things will grind to a halt at 2nm and that were in for decade of growing cowos for those that need more computing power.

    So this is probably going to be an 18a+ product maybe with a n2w gpu
    Reply
  • JRStern
    Kewl. What is IPC and why do I want it?
    Reply
  • rluker5
    Kondamin said:
    I doubt things will be going as smooth as they have for the next couple of years that things will grind to a halt at 2nm and that were in for decade of growing cowos for those that need more computing power.

    So this is probably going to be an 18a+ product maybe with a n2w gpu
    That seems like a reasonable expectation for standard EUV seeing as how the world was hung up with DUV at 14nm and barely got to 10nm and renamed it. And it already seems like the same thing is happening with EUV.
    But the high NA EUV is a sightly smaller step from EUV than EUV was from DUV so there should be some more room for improvement for fabs using high NA.
    https://www.anandtech.com/show/17415/asmls-highna-update-coming-to-fabs-in-2024-2025
    Reply
  • rluker5
    Also Intel will need a more efficient node so they can realistically run those higher IPC designs at reasonable clockspeeds.
    Remember Rocket Lake? It's a good example of increasing IPC too much without offsetting the extra power needed with a more efficient process.
    Reply
  • Kondamin
    JRStern said:
    Kewl. What is IPC and why do I want it?
    You are a member since 2017 but don’t know IPC?

    Instructions per clock, the amount of work the processor can do per tick of the clock.
    Like a truck carrying 5 tonnes of goods @70speed is able to transport more goods per unit of time than a sports car carrying a quarter even if it’s going 300speed because it needs to make more round trips.

    In cases where you just need to transport a quarter of a tonne that raw speed is better
    In other cases you want a truck.

    Ideally we would have operating systems and chips that could figure out if a task is more suited for a slow ipc heavy core or it’s better handled by a fast low ipc core

    Let’s say the fast one reading out data from a series of sensors and placing it in a spreadsheet the other one doing transformations with the total collected data.
    Reply