Alphawave, a silicon IP provider and a contract chip designer, this month teamed up with Keysight, a testing and verification equipment maker, to demonstrate interoperability of its PCIe 6.0 controller and physical interface with Keysight's testing equipment at a data transfer rate of 64 GT/s. The move verifies that Alphawave is ready to build chips with a PCIe 6.0 interface, joining a growing roster of companies that are preparing the ecosystem for the arrival of the first commercially available PCIe 6.0 devices in 2024.
Synopsys, an IP provider, has been offering its PCIe 6.0 IP package containing a controller and physical interface (PHY) since 2021, and earlier this year, the company demonstrated interoperability of its PCIe Gen6 solution with Intel's test chip.
Alphawave's silicon implementation of a PCIe 6.0 64 GT/s interface not only works with Keysight's Protocol Exerciser at full speed with pulse amplitude modulation with four levels (PAM4) signaling, but it also supports the CXL 2.0 protocol, which is an industry's first. The implementation also fully supports PCIe Gen6's Forward Error Correction (FEC), FLIT mode, and other features of the new interconnection standard. Furthermore, this PCIe Gen6 platform can be further expanded with the CXL 3.0 protocol.
"Test and measurement are critical aspects to interoperability, enabling Alphawave Semi to bring our products and customer solutions to market faster," said Letizia Giuliano, Vice President of IP Product Marketing at Alphawave Semi. "We are excited about our collaboration with Keysight, which speeds up the transition to 64 GT/s through Keysight’s state-of-the-art PCIe 6.0 protocol validation solution and instills confidence in our ability to consistently provide connectivity solutions that accelerate AI processing in high-performance computing and data infrastructure."
Synopsys licenses its IP and technologies primarily to large chip designers. By contrast, Alphawave develops bespoke chips or license technologies for smaller companies that do not tend to design or implement IP themselves. The company claims its PCIe subsystem is extremely power-efficient, offers low latency, and 'has been built off the industry's most successful PAM4 SerDes IP.' Furthermore, this PCIe Gen6 platform can be further expanded with the CXL 3.0 protocol.
