Abstract view of today's planar transistor technology in Intel semiconductors. Each transistor has only one gate.
Photograph of an actual transistor. In the current 65 nm processor generation, the gate is about 35 nm wide, the gate oxide insulator, located between the gate electrode and the silicon substrate is just 1.2 nm thin. With each new generation, the insulato
One solution to control leakage and enhance the flow of main current: Gates on three sides of the silicon substrate, not just on one.
Side-view of an actual tri-gate transistor. The main current "fin" is covered by gate insulators on three out of four sides. These tri-gate prototypes also use a "high-K" material to insulate the gate - instead of today's silicon dioxide gate dielectric.
Multiple tri-gate transistors: The gates wrap-around the current fin. Intel claims that 65 nm tri-gate transistors offer a 45% increase in speed or 50x reduction in "off"-current when compared to regular planar transistors. Tri-gate transistors could see
Tri-gate isn't the best solution. Scientists are looking for ways to build the perfect transistor, pictures in a simplified model here. The insulator (red) of the gate (green) completely wraps around the electron flow (blue) and provides a maximum of tran
The use of strained silicon in transistors is one of the current tools to increase the efficiency of electron flow and help contain current leakage. Intel first used strained silicon in 90 nm Pentium (Prescott core) and 90 nm Pentium M (Dothan core) proce
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