Nvidia's Rubin GPU and Vera CPU taped out — both chips 'in fab' at TSMC, data center AI platforms on track for 2026
Blackwell's successor hits an important milestone.

Collette Cress, chief financial officer of Nvidia, has said that the company's next-generation data center-grade GPU codenamed Rubin and CPU, codenamed Vera have been taped out and were 'in fab,' which means that their silicon is currently being produced by TSMC. The announcement indicates that Nvidia's next-generation data center platform for AI is on track for introduction in 2026.
"The chips of the Rubin platform are in fab," said Collette Kress during the company's earnings conference call with financial analysts and investors. "The Vera CPU, Rubin GPU, CX9 Super NIC, NVLink 144 scale-up switch, Spectrum X scale-out and scale-across switch, and the silicon photonics processor [for co-packages optics]. Rubin remains on schedule for volume production next year."
Having all the chips for the Rubin NVL144 rack-scale platform in the fab indicates that they have passed the important tape-out stage and Nvidia is now awaiting them in its labs to verify that they meet its performance, power, costs, and other targets.
Tape-out is a crucial milestone in semiconductor manufacturing when the final and verified chip design is sent from the design team to a chip producer for manufacturing. This stage marks completion of the physical design place-and-route process, where the chips layout has been fully optimized for performance, power, area, timings, and has passed all verification checks. Nvidia tends to simulate its designs using its own supercomputers to ensure that the very first silicon the company gets back from the fab works and achieves performance and power milestones.
At tape-out, the design is converted into a format that contains the exact geometric patterns of transistors and interconnects. This file is then used by chipmakers like TSMC to create photomasks, which are then used to make actual chips. Since mask creation is extremely costly (often tens of millions of dollars for advanced nodes), tape-out represents a critical milestone, which indicates that both logic design works as planned and the actual chip design has been simulated with acceptable results.
If mistakes are discovered after the mask printing stage, it almost certainly requires a new re-spin and tape-out, adding months of delay and tens of millions of dollars costs. So far, Nvidia's partners have successfully created photomasks and put Nvidia's Rubin GPU, Vera CPU, and various scale-up and scale-out switching ASICs to production. As soon as the company gets actual chips back from TSMC, it will begin bring up and debug processes.
Typically, if everything is fine with the first silicon implementation and no re-spins and tape-outs are required, a complex chip may enter production in 9 – 12 months. However, given that we are talking about a platform consisting of multiple chips, it will take some additional time for Nvidia and its partners to verify that all the processors work in concert as planned.
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Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.
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bit_user
I was wondering about this, recently. Does anyone have a clue how big the package is that's created, when a large modern chip tapes out?The article said:At tape-out, the design is converted into a format that contains the exact geometric patterns of transistors and interconnects. This file is then used by chipmakers like TSMC to create photomasks
(or maybe it should be tape-outs? : D)
Is it so big that they literally have to ship a stack of magnetic tapes to TSMC by overnight airmail?
My knowledge of chip design is quite dated and limited, but there at least used to be so-called "metal layer fixes" you could do, without having to recompute the higher-density photomasks. So, if you could fix something at the metal layer, that was much quicker and cheaper than a full respin.The article said:If mistakes are discovered after the mask printing stage, it almost certainly requires a new re-spin and tape-out, adding months of delay and tens of millions of dollars costs.
BTW, I was hoping to see more details about the Vera CPU, in particular. IIRC, it's an ARM core of a Nvidia in-house design.
Also, isn't Rubin supposed to be a step-change in AI compute architecture & performance?