3D Features
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| Header Cell - Column 0 | MatroxParhelia-512 | NVIDIAGF4 Ti 4600 | ATIRadeon 8500 |
|---|---|---|---|
| Chip Technology | 512-bit | 256-bit | 256-bit |
| Manuf. Process | 0.15 Micron | 0.15 Micron | 0.15 Micron |
| # of Transistors | 80 Mio | 63 Mio | 60 Mio |
| Memory Bus | 256-bit DDR | 128-bit DDR | 128-bit DDR |
| Memory Bandwith | 20 GB/s | 10,4 GB/s | 8,8 GB/s |
| AGP Bus | 1x/2x/4x/8x | 1x/2x/4x | 1x/2x/4x |
| Vertex Shader | 4 | 2 | 1 |
| Pixel Pipelines | 4 | 4 | 4 |
| Texture Stages/Pipe | 4 | 2 | 2 |
| PS Stages/Pipe | 5 | 2 | 2 |
| Texture Shader Stages | 36 | 16 | 16 |
| Vertex S. Version | 2.0 | 1.1 | 1.1 |
| Pixel S. Version | 1.3 | 1.3 | 1.4 |
| DirectX Generation | 8.0 / 9.0 | 8.0 | 8.1 |
| FSAA Modes | Fragment / SuperSampling | MultiSampling | SuperSampling |
| Z-Data Compression | - | Yes | Yes |
| Max Displays | 3 | 2 | 2 |
| Internal Ramdacs | 2 | 2 | 2 |
| External Ramdacs | 1 | - | - |
| Max Dual Resolution | 2048x1536 @ 32bpp | 1600x1200 @ 32bpp | 1600x1200 @ 32bpp |
| Max Tripple Resolution | 3840x1024 @ 32bpp | - | - |
| Bits per Color Channel | 10 | 8 | 8 |
Quad Vertex Shader Array
Parhelia has a vertex shader unit whose T&L subsystem consists of four individual shaders. Combined with a 512-unit instruction cache, 256 constant registers and optimized control, the Parhelia-512 reaches a very high vertex throughput.
The vertex shaders correspond to Microsoft's DirectX 9 (v2.0). The hardware displacement mapping engine is connected directly to the vertex shader unit, via the vertex fetcher and cache. Refer to the diagram here .
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