Matrox Parhelia-512 - The Challenger

3D Features

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Header Cell - Column 0 MatroxParhelia-512NVIDIAGF4 Ti 4600ATIRadeon 8500
Chip Technology512-bit256-bit256-bit
Manuf. Process0.15 Micron0.15 Micron0.15 Micron
# of Transistors80 Mio63 Mio60 Mio
Memory Bus256-bit DDR128-bit DDR128-bit DDR
Memory Bandwith20 GB/s10,4 GB/s8,8 GB/s
AGP Bus1x/2x/4x/8x1x/2x/4x1x/2x/4x
Vertex Shader421
Pixel Pipelines444
Texture Stages/Pipe422
PS Stages/Pipe522
Texture Shader Stages361616
Vertex S. Version2.01.11.1
Pixel S. Version1.31.31.4
DirectX Generation8.0 /
FSAA ModesFragment / SuperSamplingMultiSamplingSuperSampling
Z-Data Compression-YesYes
Max Displays322
Internal Ramdacs222
External Ramdacs1--
Max Dual Resolution2048x1536 @ 32bpp1600x1200 @ 32bpp1600x1200 @ 32bpp
Max Tripple Resolution3840x1024 @ 32bpp--
Bits per Color Channel1088

Quad Vertex Shader Array

Parhelia has a vertex shader unit whose T&L subsystem consists of four individual shaders. Combined with a 512-unit instruction cache, 256 constant registers and optimized control, the Parhelia-512 reaches a very high vertex throughput.

The vertex shaders correspond to Microsoft's DirectX 9 (v2.0). The hardware displacement mapping engine is connected directly to the vertex shader unit, via the vertex fetcher and cache. Refer to the diagram here .