Performance And Conclusion
PCMark 8 Real-World Software Performance
For details on our real-world software performance testing, please click here.
The SMI controller has reduced mixed random performance at lower queue depths, which has a real impact on application performance. We've seen this tendency many times in the past with entry-level products. Companies build controllers, even some with as many as eight cores, that perform really well with sequential data, but they lack either high random read or write performance. It's important to provide balanced performance, but companies should start by mastering random read performance.
Application Storage Bandwidth
In this chart, we combined the results of the ten PCMark 8 tests to determine the average throughput. The SM2258 with Micron 3D TLC compares well to the other products in the chart, but it's important to remember the difference of the parallelized die. In time, we will see products with this combination of components for sale and the price should be well under the current 256GB-class products. 256GB SSDs already sell for as low as $55, and we suspect that prices will dip into the $40 to $45 range before the end of the year for SSDs that use 3D flash technology.
PCMark 8 Advanced Workload Performance
To learn how we test advanced workload performance, please click here.
We discussed the slow recovery time during the sequential steady-state test, but now we get to see it in practice with real-world applications. These tests measure moderate and heavy workload performance in two states. The first phase of the test fills the drives with data to create a very dirty state (degraded), and the second phase (recovery) provides five minutes of idle time in between each test. The SM2258 doesn't recover completely in that amount of time, so its throughput performance could increase beyond what we recorded during the test.
We may also see an artificial limitation of Micron/Crucial's Dynamic Write Acceleration. The dynamic portion of the algorithm shrinks the SLC buffer as the drive fills. This test intentionally builds up dirty cells by filling the drive before it measures heavy loads, so the SLC buffer is smaller than it would be during most consumer workloads.
Total Service Time
The Crucial MX200 also suffers during the service time test, which adds weight to the theory that dynamic write acceleration issues, which we've observed with many Crucial SSDs dating back to the Micron M600, are cropping up. The M600 was the first SSD released with Dynamic Write Acceleration (DWA), and the first we tested with the feature. Crucial has used DWA technology sparingly since the M600's 2014 product release, and the feature has provided varying results in our testing.
Disk Busy Time
The disk busy time mimics the service times with minimal variation.
Notebook Battery Life
I suspect SMI has yet to optimize the SM2258 firmware for power consumption. We've tested a number of early products, both for preview articles and for private tests, to determine where a drive is during development. Power optimization and steady-state performance are usually the last stop before a controller moves to mass production (MP) firmware.
We're thankful to have the opportunity to test the SMI SM2258 controller with Micron's new 3D TLC flash. Micron hasn't delivered a lot of 3D flash to customers, so this is a rare opportunity to gauge the state of development with a combination of components we're sure to see a lot of in the future.
SMI is very close to distributing the SM2258 controller for Micron 3D TLC to SSD manufacturers. We found some behavior that indicates SMI has yet to complete some final optimization work, but the combination is mature enough to survive our testing with solid entry-level performance results.
We've discussed our early testing in other product reviews, and most of the early products fail to complete all of the tests before dying from one issue or another. We can report that our SMI SM2258 sample survived the full test suite, including our extended tests, and it still works. Taken alone, that may not seem like a big deal to many of our readers, but we usually kill three out of four early look, prototype-like SSD samples. In the last three weeks, two of three products expired during testing, and we even buried a retail product. SMI retail products have a long history of excellent service in the field, and we rarely hear of any retail SSD failures with its controllers.
Most of our observations revolve around the performance of the SMI/Micron hardware combination. We discussed the 384Gbit die and how it hurts parallelization and performance in low capacity SSDs, and the 240GB drive we tested is a good example of the issue because it is equivalent to the modern 64GB SSDs that ship with a 128Gbit die. We wouldn't even test a 64GB SSD today, and we try to avoid 128GB drives. We will take a serious look at removing 256GB-class SSDs from our charts in 2017. When the time comes to exit the 256GB market, the prices will be very low. We suspect Micron 3D TLC-enabled SSDs for the entry-level market will drop into the $40 range by the end of the year. The price is right, but the performance won't be sufficient for most of our readers.
Crucial recently disclosed the remaining capacities and performance for the MX300 series. The MX300 275GB lists performance at 530/500 MB/s sequential read/write, which is less than what Silicon Motion managed with the SM2258 controller. Even in this early stage of development, the SM2258 controller also managed to outperform the MX300 275GB in random performance tests. We were surprised to learn that Crucial chose the Marvell Dean controller to pair with 3D TLC in its MX300 series. Now we know that, other than speeding time to market, it may not have been the best option available.
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tlc have 3-bit cells. there are 8 levels of states (not sure if these are volts or amps), each level give a binary number between 000 and 111, so can represent 3 independent bits. To have 2 independent bits, you only need to reliably distinguish 4 states, which is obviously easier, but the 66% less memory per density.