Intel's March 30 release of the Xeon 7500-series is significant in more ways than one. Publicly, the company is boasting of taking its 30-year-old x86 architecture into new ground--the mission-critical space previously dominated by mainframes and RISC-based systems like Sun's SPARC and IBM's POWER processors.
The Xeon 7500 is not intended as a file and print or Web server. You can use a low-power Xeon 3400 or even a Core i7 for that. The 7500 is aimed at the high-performance market of servers that must stay up and running with no downtime and have the capacity to handle thousands of simultaneous users. It's new territory for x86, but not for Intel.
Intel is already in that space with its other architecture, the EPIC architecture in the Itanium. EPIC is not technically RISC in design, but is frequently lumped into that category. While Intel has not said publicly that the Xeon 7500 will replace the Itanium, and no one is expecting it to in the short run, the Xeon 7500 does show that Intel has the ability to continue to evolve the x86 architecture and move it up the performance food chain.
The Xeon 7500 family, developed under the codename "Nehalem-EX," is a monster of a chip, with 2.3 billion transistors used in eight cores connected with high-speed interconnects, four very fast memory channels, and Hyper-Threading, allowing each core to run two threads at a time. It adds more than 20 features that have been in the Itanium for some time, giving the Xeon 7500-series levels of performance and reliability other Xeons can't match.
The Itanium has never been a big seller for Intel, but the few machines that were sold were absolutely valuable. Itanium was used in servers that defined "mission-critical." They had to run 24x7 and not be brought down by a crash. Itanium servers were usually multi-million dollar beasts that ran multi-petabyte Oracle databases or line-of-business applications that had to always run.
This meant something known as RAS: reliability, availability and serviceability. The Xeon 7500 has more than 20 new RAS features normally found in Itanium processors, marking the first time they have been used in a Xeon.
The most significant among them is Machine Check Architecture (MCA) Recovery, a feature that allows the CPU to work with the operating system to isolate errors that would otherwise crash the machine and keep the machine operating. Other features include memory corruption protection like SMI Lane Failover to handle memory errors and QPI self-healing for errors during interprocessor communication.