Zvi Or-Bach, chief executive of MonolithIC 3D, a 3D semiconductor integration company, presented an analysis back in 2014 that shows that per-transistor cost has stopped decreasing at 28nm. Recently, this finding was corroborated by Milind Shah from Google, who demonstrated that the per-transistor cost for 100 million gates had actually increased since 2012 when a 28nm planar process technology was put into mass production by TSMC, reports Semiconductor Digest.
"Transistor cost scaling (0.7X) stalled at 28 nm and remains flat gen-over-gen," the Google finding shows.
The industry has been concerned about diminishing returns for per-transistor costs with new nodes for quite a while. The latest chipmaking process technologies — such as 7nm, 5nm, and 3nm — require more sophisticated fab tools that cost hundreds of millions (how about $200 million in the case of an ASML Twinscan NXE litho machine?), which brings the cost of leading-edge fabs to levels from $20 billion to $30 billion. This, of course, makes production at leading-edge nodes very expensive. However, while chipmaking has gotten more complex and expensive over the years, it makes sense to take a look at the bigger picture here.
Indeed, based on the graph presented by Milind Shah from Google at the industry tradeshow IEDM, the cost of 100 million transistors normalized to 28nm is actually flat or even increasing. This lack of cost scaling makes it less appealing for some chip designs to adopt some of the latest nodes. Furthermore, it makes it more appealing to disaggregate some designs, i.e., chop them up into chiplets, instead of producing monolithic designs crafted of a single piece of silicon using a leading-edge node to optimize costs and performance.
AMD's Ryzen desktop CPUs and Intel's Meteor Lake laptop CPUs are the most obvious example of disaggregated designs in client computing space, which consist of three or four chiplets made on different process technologies at different factories. In the data center realm, AMD's epically successful EPYC data center CPUs serve as another example. Multi-billion companies like AMD and Intel can certainly assess their design options carefully and then build products using the best technologies in their possession. For smaller makers, things may not be that easy.
First up, multi-chiplet designs tend to be more power-hungry than monolithic designs, so they aren't exactly the best choice for mobile devices. Secondly, multi-chiplet integration is a tough engineering task, and while companies like MonolithIC 3D offer their multi-chiplet integration services (ultimately using advanced packaging technologies, such as Intel's Foveros or TSMC's CoWoS), their services cost money. Thirdly, advanced packaging technologies are expensive, and getting CoWoS allocation is as hard as getting a leading-edge node allocation.
To that end, while new nodes may no longer make transistors cheaper, they still make a lot of sense for many designs that either cannot be disaggregated efficiently or are hard to disaggregate due to complications with their manufacturing.
