PCI-SIG announces PCIe 8.0 spec with twice the bandwidth — 1TB/s of peak bandwidth, 256 GT/s per lane, and a possible new connector

The PCI-SIG consortium has officially announced the development of the PCI Express 8.0 specification. This new version is set to double data transfer rate to 256 GT/s per lane. In addition to the extra bandwidth, PCIe Gen8 is said to feature protocol enhancements to increase real-world bandwidth and reduce power consumption.

The upcoming PCIe 8.0 specification will double the raw bit rate of PCIe 7.0 to 256.0 GT/s, enabling up to 1 TB/s of bi-directional bandwidth across a x16 configuration. The spec will continue to rely on PAM4 signaling with forward error correction (FEC) and Flit Mode encoding, which have been used with PCIe 6.0 and PCIe 7.0. However, hitting 256 GT/s per lane will likely be an incredibly difficult task. Engineers will enter uncharted territory, as no current copper interconnect standard can boast such a data transfer rate, especially over distances of tens of centimeters.

To ensure reliability, a usable signal-to-noise ratio, consistent performance, acceptable signal loss, signal integrity, and power efficiency for PCIe 8.0 interconnections, PCI-SIG is now reviewing a new interconnection technology while maintaining backwards compatibility with previous-generation PCIe implementations. The specification is also set to introduce protocol enhancements to optimize bandwidth use, and methods to improve power efficiency.

PCI-SIG's release does not explicitly say whether all PCIe Gen 8 implementations will continue to rely on copper, though backwards compatibility implies plans to continue using copper interconnects. At 256 GT/s over copper, designers face extreme signal integrity challenges, length constraints, and a heavy dependency on materials, equalization, retimers or alternative transmission methods.

These issues are pushing the industry toward optical interconnects and advanced packaging (like co-packaged optics or chiplets with short-reach links) for future high-speed systems. These needs are why PCI-SIG has issued optical-aware retimer specifications for PCIe 6.4 and 7.0, which will likely extend to PCIe 8.0.

"Following this year's release of the PCIe 7.0 specification, PCI-SIG is excited to announce that the PCIe 8.0 specification will double the data rate to 256 GT/s, maintaining our tradition of doubling bandwidth every three years to support next-generation applications," said Al Yanes, PCI-SIG President and Chairperson. "With the increasing data throughput required in AI and other applications, there remains a strong demand for high performance. PCIe technology will continue to deliver a cost-effective, high-bandwidth, and low-latency I/O interconnect to meet industry needs."

As is usual with the recent generations of PCIe announcements, PCI-SIG positions its next-generation interconnection technology primarily for high-end, bandwidth-hungry applications like AI servers and data centers, HPC workloads, hyperscale cloud service providers, and automotive, aerospace and military solutions. While client PCs might eventually adopt PCIe 8.0, timelines for such applications will likely extend well into 2030s at the earliest.

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